Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-07
2003-02-11
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06518131
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application claims the priority of Korean patent application Serial No. 2001-51827 filed on Aug. 27, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a mask ROM, and in particular to an improved method for fabricating a mask ROM which can apply a dual gate process and a salicide process of a logic process to a flat cell type mask ROM.
2. Description of the Background Art
A mask ROM is a non-volatile device which uses a mask process in an element isolation process, a metal process or an ion implant process for a channel region of a memory cell. For example, a threshold voltage difference is generated between a memory cell where the ion implant process is performed and a memory cell where the ion implant process is not performed. By using such a difference, the mask ROM discriminates data and records necessary information.
FIG. 1
is a layout diagram illustrating a conventional cell array.
A flat cell type mask ROM has been widely used in a fabrication method using a logic process.
Referring to
FIG. 1
, in the fabrication process of the flat cell type mask ROM, an isolation process is performed at the outer portion of a memory cell array region
10
to surround the whole memory cell array region
10
, instead of performing a LOCOS or STI process for isolating memory cells. A source/drain junction of the memory cell is a buried layer
116
formed before the gate process. It is thus unnecessary to isolate the junctions. A contact hole
150
of the buried layer junction does not exist in the memory cell array region
10
but in a segment select region
20
. In addition, a gate
125
is formed in an orthogonal direction to the buried layer junction, and a width of the gate
125
is a channel width of the memory cell.
As described above, an isolating pattern and a contact hole are not formed in the memory cell, and thus a size of the memory cell is about 4F
2
(‘F’ implies a minimum line width of photolithography), thereby improving integration, simplifying the whole process and cutting down production costs.
When a logic process of a design rule below 0.35 &mgr;m is applied to the fabrication process of the flat cell type mask ROM, 1) the isolation process is performed by LOCOS, 2) N type impurity-doped polysilicon, Ti-Salicide or W-Polycide is used as the gate formation material, and 3) Ti-Salicide identical to the gate formation material is employed as the source/drain junction.
In addition, when the flat cell type mask ROM is fabricated according to a logic process of a design rule below 0.25 &mgr;m, 1) the isolation process is performed to surround the whole memory cell array region by a trench STI, 2) Ti-Salicide or Co-Salicide is used as the gate formation material, and 3) Ti-Salicide or Co-Salicide identical to the gate formation material is employed as the source/drain junction.
Accordingly, the flat cell type mask ROM having compatibility with the logic process of a design rule below 0.35 &mgr;m has been commercially used. There are therefore increasing demands for a flat cell process having compatibility with the logic process below 0.25 &mgr;m.
FIG. 2
is a flowchart showing a conventional process for fabricating a mask ROM.
As illustrated in
FIG. 2
, the conventional method for fabricating the mask ROM includes: an isolation process for forming an element isolating film at the outer portion of a memory cell array region; a well formation process; a buried layer formation process; a process for forming a gate insulating film and gates in the memory cell array region and its peripheral region; a cell isolation ion implant process for implanting ions to the memory cell array region; a process for forming a source/drain in the gates of the peripheral region; a coding process; a process for forming a contact hole in a buried layer of a segment select region; and a bit line formation process.
FIGS. 3
a
through
3
f
are cross-sectional diagrams illustrating sequential steps of the conventional method for fabricating the mask ROM, taken along lines A-B and C-D of FIG.
1
. In
FIGS. 3
a
to
3
f,
region ‘I’ denotes a section taken along line A-B, and regions ‘II’, ‘III’ denote sections taken along line C-D.
The conventional method for fabricating the mask ROM will now be described by using the logic process of a design rule below 0.35 &mgr;m.
As depicted in
FIG. 3
a,
provided is a substrate
100
where a memory cell array region I+II and a peripheral region III formed at the outer portion of the region
10
are defined.
An element isolating film
103
is formed at the outer portion of the memory cell array region I+II of the substrate
100
according to a LOCOS process.
Thereafter, a well
102
is formed on the substrate
100
having the element isolating film
103
. At this time, the element isolating film formation process and the well formation process may be performed in an inverse order.
As illustrated in
FIG. 3
b,
a photoresist film is coated on the substrate
100
having the element isolating film
103
and the well
102
, and exposed and developed to form a first photoresist film pattern
104
opening a predetermined region. Here, a buffer oxide film
105
is positioned between the substrate
100
and the first photoresist film pattern
104
.
An N-type As
+
ion implant process
106
is performed on the substrate
100
by using the first photoresist film pattern
104
as a mask. Reference numeral
108
denotes an As
+
ion layer implanted to the substrate
100
at a predetermined depth.
Then, the first photoresist film pattern
104
is removed, and a thermal treatment (not shown) is carried out on the As
+
implanted substrate
100
. Here, As
+
ions are diffused according to the thermal treatment, thereby forming a buried layer
116
. At the same time, an oxide film
112
is formed on the buried layer
116
.
Referring to
FIG. 3
c,
a gate oxide film
122
and a gate formation material layer
125
are sequentially formed on the substrate
100
having the buried layer
116
and the oxide film
112
. The gate formation material layer
125
is formed by sequentially depositing a silicon layer such as a doped polysilicon or amorphous silicon layer, a metal layer such as a Ti or W layer having a low resistance value for high speed signal transmission, and a nitride film.
As illustrated in
FIG. 3
d,
a second mask pattern (not shown) covering the gate formation region of the peripheral region III and the memory cell array region I+II is formed on the formation material layer
125
. The gate formation material layer
125
is etched by using the second mask pattern, to form gates
125
in the memory cell array region I+II and the peripheral region III. When the gate formation material layer
125
is etched, an exposed silicon region
126
is an interval between memory cell channels.
A photoresist film is coated on the substrate
100
, and exposed and developed to form a third photoresist film pattern
130
exposing the memory cell array region
10
and covering the peripheral region III.
An ion implant process for cell isolation
132
is performed on the intervals
126
between the channels of the memory cell array region I+II, by using the third photoresist film pattern
130
as a mask. The third photoresist film pattern is removed. As shown in
FIG. 3
e,
a photoresist film is coated on the substrate
100
, and exposed and developed to form a fourth photoresist film pattern
134
covering the memory cell array region I+II and exposing the peripheral region III.
Thereafter, LDD ions are implanted to the substrate
100
at both sides of the gate
125
of the peripheral region III, by employing the fourth photoresist film pattern
134
as a mask. An insulating spacer
138
is formed at the side walls of the gate
125
. A source/drain impurity implant process
136
is performed on the substrate
100
by using the insulating spacer
138
including the gate
125
as a mask, thereby forming a source/drain.
A dat
Dongbu Electronics Co. Ltd.
Keefer Timothy J.
Tsai Jey
Wildman Harrold Allen & Dixon
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