Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-10-19
2003-02-11
Lee, Thomas (Department: 2154)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S500000, C713S600000
Reexamination Certificate
active
06519709
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method of synchronizing clock and device for use in such method to output data inputted in synchronization with a first clock in synchronization with a second clock which can be used suitably, for example, for a computer network.
2. Description of the Related Art
In some of conventional local area networks (LAN), as shown in
FIG. 12
, personal computers
31
1
and
31
2
are connected through packet assembling and disassembling devices
32
1
and
32
2
, interfaces
33
1
and
33
2
and packet sending/receiving devices
34
1
and
34
2
to a network
35
of LAN. In LANs, a packet is used to send or receive data between a personal computer and the network
35
of LANs.
In some cases of transmission of packets, though there is no difference in frequency between a clock signal of an input packet and that of an output packet, a variation exists between a frequency of the clock signals of the input packet and that of the output packet. Also, in some cases, even if there is the difference as described above, there is a variation between a frequency of the clock signal of the input packet and that of the output packet. In such a case, in order to correctly pass an inputted packet to an output side, it is vital to output data inputted in synchronization with the input clock in synchronization with the output clock (i.e., it means that a clock of data is converted from the input clock to the output clock). However, in the case of sequence data such as a packet, a conversion of a clock is impossible by detection of a rise or fall of a pulse due to omission or duplication of data.
Because of this, as shown in
FIG. 13
, packet assembling/disassembling devices
32
1
and
32
2
of a LAN are provided with a clock synchronizing circuit used to convert a clock. As depicted in
FIG. 13
, the clock synchronizing circuit contains a memory
42
, a write pointer generating circuit
45
, a data termination detecting circuit
46
and a read pointer generating circuit
47
. At the start of the conversion of a clock, the memory
42
is initialized and, at the same time, the write pointer generating circuit
45
initializes a write pointer in response to an input clock and generates an initialized write pointer, while the read pointer generating circuit
47
initializes a read pointer in response to an output clock and generates an initialized read pointer (Step SQ
1
and SQ
2
in FIG.
14
). Until a packet data is inputted to a write input of the memory
42
, the generated write pointer is not renewed (Step SQ
3
). When the packet data is inputted (Step SQ
3
), the memory
42
writes, in response to the input clock signal, a write data unit out of the inputted packet data into a storage position designated by the write pointer outputted from the write pointer generating circuit
45
(Step SP
4
). Then, the write pointer is renewed (Step SQ
5
).
Every time the write pointer is renewed, a judgement on whether writing of all packet data is terminated or not is made by a data termination detecting circuit
46
(Step SQ
6
). If the writing is not terminated, a subsequent write data unit of the packet data is written into a write position of a memory
42
designated by the write pointer renewed by the write pointer generating circuit
45
.
If the judgement on termination of writing the packet data is positive (in the case of “YES” of Step SQ
6
), a packet write termination instructing signal is generated (Step SQ
7
) and a signal for processing packet reading is fed and, at the same time, in the packet writing processing, the operation returns back to Step SQ
3
which is in the waiting state for inputting of packet data and to wait for inputting of a subsequent packet data.
At the same time when the packet writing processing is in the state of waiting for packet data, reading processing that had been in the standby state is started in response to the packet writing termination instructing signal (in the case of “YES” in Step SQ
8
) When this packet reading processing is started, a read data unit of the packet is read from the reading position of the memory
42
designated by the read pointer that had been initialized (Step SQ
9
) and the read data unit is outputted as a first read data unit of the packet written in the memory
42
. At the same when this reading is carried out, the read pointer is renewed to be a read pointer having a subsequent data unit (Step SQ
10
).
Every time such reading pointer is renewed, a judgement on whether reading of packet data is terminated or not is carried out (Step SQ
11
). If it is not terminated (in the case of “NO” in Step SQ
11
), a subsequent read data unit of packet data is read from a reading position of the memory
42
designated by the renewed read pointer.
If the judgement on termination of reading the packet data is positive (in the case of “YES” of Step SQ
11
), the operation returns back to Step SQ
8
being in the standby state for the start of the packet reading and to wait for a packet writing termination instructing signal of the subsequent packet until a signal of informing the termination of writing the packet is received. Thus, the above procedure allows data inputted in synchronization with an input clock to be outputted in synchronization with an output clock (i.e., when data is inputted or outputted, a clock of data can be converted from the input clock to the output clock).
However, as described above, though the conventional synchronizing circuit allows packet data inputted in synchronization with an input clock to be outputted in synchronization with an output clock, in order to achieve the synchronization, only one technique is available wherein, after a whole packet is written into the memory
42
by an input clock signal having the number of writing units constituting one packet, the packet is read by the output signal having the number of reading units constituting the packet. However, this technique suffers a shortcoming that one packet of storage capacity is unavoidably required for outputting packet data inputted in synchronization with an input clock to be outputted in synchronization with an output clock, thus causing a delay of sending and receiving a packet caused by a temporary storage. Moreover, another disadvantage is that a major portion of a chip area is occupied by the synchronizing circuit in integration process on a semiconductor chip.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide method of synchronizing clock and device for use in such method which allows a reduction in storage capacity required for outputting data inputted in synchronization with an input clock in synchronization with an output clock, thus achieving simplification, miniaturization and drop in prices of the synchronizing device.
According to a first aspect of the present invention, there is provided a method of synchronizing a clock for transferring data from a first circuit operated at a first clock through a storing means being accessible independently to its input and output to a second circuit operated by a second clock comprising the steps of:
storing data fed by the storing means;
detecting whether data stored in the storing means is effective data;
renewing, if a decision is positive, an access pointer of the storing means in response to the clock;
re-initializing, if a decision is negative, the access pointer of the storing means in response to the clock; and
outputting data inputted in synchronization with the first clock in synchronization with the second clock by accessing the storing means using the access pointer.
In the foregoing, a preferable mode is one wherein a frequency of first clock is different from that of second clock.
Also, a preferable mode is one wherein width of storage capacity N of the storing means is a sum of a width of storage capacity given by a following formula (1) derived in the case where an output clock is faster than an input clock and a width of storage capacity given by a following
Hu Jinsong
Lee Thomas
NEC Corporation
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