Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus expansion or extension
Reexamination Certificate
1999-11-12
2003-02-25
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus expansion or extension
C327S530000
Reexamination Certificate
active
06526466
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to interconnecting integrated circuits while power connections are active (hot swapping), and particularly to hot swapping programmable logic devices.
BACKGROUND OF THE INVENTION
Hot swapping refers to the insertion or removal of electronic components, such as integrated circuits or circuit boards, into or from powered-up systems. CompactPCI, PCMCIA, Universal Serial Bus (USB), SCSI, and other standards provide strict mandates on leakage current and other power-up/power-down aspects of hot swapping. Hot swapping an ill-designed integrated circuit can adversely affect system operation.
There are a number of integrated circuits commercially available for providing hot swap compatibility. However, such integrated circuits must be included on a circuit board with a plurality of other devices. Therefore, an on-chip solution for hot swapping is still needed.
One type of electronic component in need of an on-chip hot swap solution is the programmable logic device (PLD), such as the field programmable gate array (FPGA). An FPGA includes configurable logic blocks (CLBs) to construct the user's logic, input/output blocks (IOBs) to provide the interface between the package pins and internal signal lines, and programmable interconnect to connect the input and output terminals of the above-referenced blocks to the appropriate networks. The functionality of the FPGA is customized during configuration by programming internal memory cells associated with the CLBs, IOBs, and programmable interconnect. Additional information regarding FPGAs can be found in “The Programmable Logic Data Book”, pages 4-11 to 4-49, published by Xilinx, Inc. in 1999.
FIG. 1
illustrates a portion of an IOB
100
including an input buffer
102
, a tristate output buffer
104
, and a pull-up transistor
110
. During power-up and configuration (hereinafter referred to only as configuration) of the FPGA, the signal on line
109
is a logic one. In this manner, NOR gate
111
provides a logic zero signal (i.e. the signal on line
112
is a “don't care”) to the gate of pull-up transistor
110
, thereby turning on p-type transistor
110
and pulling up I/O pad
101
to voltage Vcc. The logic one signal on line
109
is inverted by inverter
108
and provided to NAND gate
106
. Thus, NAND gate
106
outputs a logic one signal (i.e. the signal on line
107
is a “don't care”), thereby ensuring output buffer
114
is in a high impedance mode (tristated).
Because a logic signal (in this case, a logic one signal) is provided on I/O pad
101
, input buffer
102
does not draw static current during configuration of the FPGA. Note that the logic signal provided to input buffer
102
further ensures that internal circuits in the FPGA receive a constant signal which minimizes any on-chip disturb conditions during the configuration mode. This logic signal also minimizes any adverse effect to the external circuits or systems coupled to I/O pad
101
during the configuration mode of the FPGA.
After configuration is complete (the user mode), the signal on line
109
is a logic zero. In this state, pull-up transistor
110
is controlled by the signal on line
112
. Typically, pull-up transistor
110
is turned on (a logic one signal on line
112
) only if tristate output buffer
104
is in a high impedance mode. Otherwise, pull-up transistor
110
is turned off (a logic zero on line
112
).
Because the signal on line
109
is a logic zero, tristate output buffer
104
is controlled by the signal on line
107
. If the signal is a logic one, then tristate (active low enable) output buffer
104
functions as a normal buffer. In this configuration, IOB
100
is used as an output block or a dual function (input/output) block. If the signal is a logic zero, then output buffer
104
is tristated and IOB
100
is used as an input only block.
Referring to
FIG. 2
, a hot swappable board
200
connects I/O pad
101
to a one-volt supply Vp across a ten thousand Ohm (10 k Ohm) resistor
205
. In accordance with hot swap specifications, this one-volt supply Vp must precharge I/O pad
101
to an intermediate voltage level before contact with a backplane
210
. This precharging reduces noise on backplane
210
. However, any voltage difference between voltage Vp and the voltage on I/O pad
101
(Vcc) during a hot swap induces a leakage current IL through pull-up transistor
110
. Current hot swap specifications have extremely tight restrictions on leakage current. For example, assuming I/O pad
101
is pulled to voltage Vcc (or even to ground in other embodiments), the resultant leakage current I
L
could be from two to twenty-five times the acceptable limit of most hot swap specifications.
Therefore, a need arises for a way to enable hot swapping of PLDs and boards including PLDs, while still preventing the input buffers in the IOBs from drawing static current during device configuration and providing appropriate signals to the internal circuits of the PLDs.
SUMMARY OF THE INVENTION
The present invention provides a hot swap circuit that eliminates any leakage current, ensures no static current occurs, and provides appropriate signals to the internal circuits of the PLD. In accordance with the present invention, the hot swap circuit forms part of an input/output block of a PLD. The hot swap circuit includes an input buffer disable circuit and an output buffer disable circuit, both disable circuits coupled to a pad of the PLD.
The output buffer disable circuit includes an output buffer for providing signals to the pad and a first logic circuit having an output terminal coupled to an enable terminal of the output buffer. During power-up or configuration, the first logic circuit disables (tristates) the output buffer. In accordance with the present invention, the output buffer disable circuit further includes a second logic circuit having an output terminal coupled to a gate of a transistor. The transistor is coupled between a voltage source and the pad. In one embodiment, the transistor is a pull-up transistor coupled between voltage Vcc and the pad. During a hot swap, the second logic circuit turns off this pull-up transistor, thereby providing a critical floating voltage on the pad that eliminates any leakage current. Thus, the present invention advantageously conforms to all current hot swap specifications.
The input buffer disable circuit comprises an input buffer for receiving signals from the pad and a third logic circuit operatively coupled to the input buffer to selectively disable the input buffer and provide a predetermined voltage on the output terminal of the input buffer. The input buffer includes a first inverter and a second inverter connected in series. A pull-down transistor is coupled between the output terminal of the first inverter and ground. The gate of the pull-down transistor is coupled to the third logic circuit. During power-up and configuration, the third logic circuit disables the first inverter (and thus the input buffer) and turns on the pull-down transistor, thereby ensuring no static current is generated and providing a constant, known signal to the internal circuits of the PLD.
After configuration is complete (the user mode), the third logic circuit enables the input buffer. However, second and third logic circuits can selectively turn on the pull-up transistor and disable the output buffer, respectively.
Because each of the input buffer, the output buffer, and the pull-up transistor are selectively controlled, the present invention advantageously enables full backward compatibility with previous design solutions involving the PLD.
REFERENCES:
patent: 5900021 (1999-05-01), Tiede et al.
patent: 6127882 (2000-10-01), Vargha et al.
patent: 6138195 (2000-10-01), Bermingham et al.
patent: 6339343 (2002-01-01), Kim et al.
patent: 6400203 (2002-06-01), Bezzi et al.
“The Programmable Logic Data Book”, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, 1999, pp. 4-11 to 4-49.
“The Programmable Logic Data Book”, available from Xilinx,
Frake Scott O.
McManus James L.
Schultz David P.
Yee Wilson K.
Auve Glenn A.
Harms Jeanette S.
Kubodera John
Xilinx , Inc.
Young Edel M.
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