Method of forming an array of FLASH field effect transistors...

Details Method of forming an array of FLASH field effect transistors... Method of forming an array of FLASH field effect transistors...

2003-02-27

2003-11-11

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06645814

ABSTRACT:

TECHNICAL FIELD
This invention relates to a method of forming an array of FLASH field effect transistors and circuitry peripheral to such array.
BACKGROUND OF THE INVENTION
Memory is but one type of integrated circuitry. Some memory circuitry allows for both on-demand data storage and data retrieval. For example, memories which allow both writing and reading, and whose memory cells can be accessed in a random order independent of physical location, are referred to as random-access memories (RAM). Read-only memories (ROMs) are those in which only the read operation can be performed rapidly. Entering data into a read-only memory is typically referred to as programming, and the operation is considerably slower than the writing operation utilized in random-access memory. With random-access memory, information is typically stored with respect to each memory cell either through charging of a capacitor or the setting of a state of a bi-stable flip-flop circuit. With either, the stored information is destroyed when power is interrupted. Read-only memories are typically non-volatile, with the data being entered during manufacturing or subsequently during programming.
Some read-only memory devices can be erased as well as written to by a programmer. Erasable read-only memory typically depends on the long-term retention of electronic charge as the information storage mechanism. The charge is typically stored on a floating semiconductive gate, such as polysilicon. One type of read-only memory comprises FLASH memory. Such memory can be selectively erased rapidly through the use of an electrical erase signal.
A FLASH memory cell typically comprises a single floating gate transistor. For multiple storage cells, such as used in large semiconductor memories, the storage cells of the memory are arranged in an array consisting of rows and columns. The rows are typically considered as comprising individual conductive gate lines formed as a series of spaced floating gates received along a single conductive line (hereafter referred to as “a line of floating gates”). Source and drain regions of the cells are formed relative to active area of a semiconductor substrate, with the active areas being generally formed in lines running substantially perpendicular to the lines of floating gates. The sources and drains are formed on opposing sides of the lines of floating gates within the active area with respect to each floating gate of the array. Thus, lines (rows) of programmable transistors are formed.
Electrical connections are made with respect to each drain to enable separate accessing of each memory cell. Such interconnections are arranged in lines comprising the columns of the array. The sources in FLASH memory, however, are typically all interconnected and provided at one potential, for example ground, throughout the array. Accordingly, the source regions along a given line of floating gates are typically all provided to interconnect within the substrate in a line running parallel and immediately adjacent the line of floating gates. These regions of continuously running source area are interconnected outside of the array, and strapped to a suitable connection for providing the desired potential relative to all the sources within the array.
FLASH memory fabrication typically includes an array of FLASH field effect transistors and circuitry which is peripheral to the array. Array FLASH field effect transistors and periphery field effect transistors typically have different gate dielectric or gate oxide thicknesses, and accordingly, are typically fabricated at different times. Usually, the periphery gate dielectric is generally thicker than the array gate dielectric due to higher voltage operation of periphery transistors as compared to that of the array. The periphery gate dielectric can be fabricated after the fabrication of the array gate dielectric. Unfortunately, this results in the typical isolation oxide within the periphery being subjected to a greater quantity of oxide etchings than occurs relative to the isolation oxide within the array. This can result in significant exposure of a corner of silicon where the active area meets the substrate isolation where a transistor gate passes from over active area to over isolation oxide. This can adversely affect the circuitry in operation.
FIG. 1
depicts the problem just described. A semiconductor wafer fragment
10
is shown as appearing in a periphery circuit area to an array of FLASH field effect transistors (not shown) being fabricated. Such comprises a bulk active area substrate region
11
having an adjacent region of trench isolation oxide
12
. To produce the active area and trench or other field isolation, typical prior art processing would first deposit a pad oxide layer over the substrate and then a silicon nitride comprising layer thereover. The pad oxide and silicon nitride layer would be patterned and etched relative to the bulk substrate to define and form exposed isolation areas of the bulk substrate. With trench isolation, trenches would be etched into the bulk substrate and subsequently filled with an insulative isolation material, for example silicon dioxide. The substrate is then polished and/or etched effective to remove at least the masking silicon nitride and expose or etch through the pad oxide. The periphery is then masked, typically with photoresist, with the array left exposed. One or more conductivity modifying implants are then conducted into semiconductive material of the substrate within the array. Exemplary such implants include V
t
threshold implants and channel enhancement implants.
The mask is subsequently stripped and the entire substrate subjected to a thermal oxidation to form a sacrificial oxide. Typically, such oxide is grown to correct defects and otherwise improve the semiconductive material substrate outer portion/surface for a subsequent gate oxide growth. Thereafter, the sacrificial oxide and any remaining pad oxide are stripped from the substrate. Gate oxide is then formed which is optimized for the array, but/and also grows over the periphery in a blanket manner. Floating gate material is then deposited, with the array then being patterned in at least one dimension towards formation of the floating gates. In such patterning, all such floating control gate material and the gate dielectric are typically etched from the periphery.
Next, another gate dielectric (typically an oxide-nitride-oxide composite) is formed over the control gate material within the array, and accordingly, blanketly over the substrate and, therefore, within the periphery. The array is then masked, and then the gate dielectric formed in the periphery is stripped.
All of the above-described sacrificial oxidation stripping, first gate oxide stripping and second gate oxide stripping within the periphery has a tendency to form a recess
13
(
FIG. 1
) where isolation oxide
12
meets with active area bulk semiconductive material
11
. Typically, a gate oxide layer
14
is formed next, optimized for the periphery field effect transistors. Such can result in the illustrated gate oxide thinning over the active area bulk material corner. This can lead to adverse operation of the circuitry in operation.
The invention was motivated in addressing the above-described issues and improving upon the above-described drawbacks. However, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification or the drawings) and in accordance with the doctrine of equivalents.
SUMMARY
The invention includes methods of forming an array of FLASH field effect transistors and circuitry peripheral to such array. In one implementation, thermal oxidation of a peripheral area of a semiconductor substrate is globally restricted with an overlying oxidation resistant layer that is not globally received within the array during formation of a sacrificial oxide layer prior to forming any transistor gate

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