Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-05
2003-12-16
Potter, Roy (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S313000
Reexamination Certificate
active
06664157
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and to a method of producing the same. More specifically, the invention relates to technology that can be effectively applied to a semiconductor integrated circuit device having a DRAM (dynamic random access memory).
Memory cells in a DRAM are generally arranged at intersecting points of plural word lines and plural bit lines that are arranged in the form of a matrix on a main surface of a semiconductor substrate. Each memory cell is constituted by a MISFET (metal insulator semiconductor field-effect transistor) that selects it and a data-accumulating capacitor element (capacitor) connected in series with the MISFET.
The MISFET for selecting the memory cell is formed in an active-region surrounded by a device isolation region, and it is constituted chiefly by a gate oxide film, a gate electrode formed integrally with a word line, and a pair of semiconductor regions forming a source and a drain. Two MISFETs are usually formed in one active region, and the source and drain (semiconductor regions) of one of the two MISFETs are shared at the central portion of the active region. A bit line is arranged on the MISFET and is electrically connected to the semiconductor regions that are shared. The capacitor is arranged on the MISFET and is electrically connected to the other source and drain.
In a DRAM having a capacitor-over-bit-line (COB) structure in which the capacitor is arranged on the bit line, the lower electrode (accumulator electrode) of the capacitor arranged on the bit line is formed to have a cylindrical shape, and a capacitor insulating film and an upper electrode (plate electrode) are formed on the lower electrode. The lower electrode is formed to have a cylindrical shape to increase the surface area thereof, in an attempt to compensate for a reduction in the electric charge (Cs) accumulated in the capacitor caused by the fact that the memory cell is finely formed. In the memory cell having a COB structure as described above, the capacitor must be constructed to have a three-dimensional structure to a conspicuous degree from the standpoint of maintaining reliable operation as a semiconductor memory device.
Even by constructing the capacitor to have a three-dimensional structure, a difficulty can be expected in maintaining the required capacitance (accumulated electric charge) in modern integrated semiconductor devices and, particularly, in the DRAMs produced after those corresponding to 256 Mbits (megabits).
A study has been made of the use of a highly dielectric material (ferroelectric material), such as tantalum oxide (Ta
2
O
5
), STO (SrTiO
3
) or BST (Ba
x
Sr
1−x
TiO
3
), as an insulating film for a capacitor, as described in “Applied Physics”, Vol. 65, No. 11, published by Japanese Academy of Applied Physics, Nov. 10, 1996, pp. 1111-1112. Ta
2
O
5
has a specific inductive capacity of as high as about 40, and STO and BST have specific inductive capacities that are very high, such as about 200 to 500. By using these films having high specific inductive capacities, therefore, it becomes easy to realize a large capacity compared to use of the traditionally used silicon oxide film and silicon nitride film. In particular, STO and BST exhibit high dielectric constants, and a greatly increased capacity can be expected.
The lower electrode of the capacitor is connected to the source and drain of the MISFET through a plug, and a reaction-preventing layer is formed for preventing the reaction of ruthenium forming the lower electrode with a plug material (silicon).
SUMMARY OF THE INVENTION
When a DRAM having the above structure is highly densely integrated, however, there occurs a problem of deviation in matching relative to an underlying silicon plug at the time of patterning the lower electrode of the capacitor. That is, in the highly dense DRAMs produced after the 256-megabit DRAM, the size of the silicon plug in the transverse direction is nearly equal to the size of the lower electrode in the transverse direction. In such a dimensional region, the pattern of the lower electrode is deviated relative to the underlying pattern (silicon plug) at the time of effecting the patterning for forming the lower electrode, relying upon photolithography. Due to this deviation in matching, the plug member is partly exposed. The presence of the exposed portion permits the dielectric (capacitor-insulating film) to come into direct contact with the plug member, whereby a leakage current increases, making it no longer possible to accomplish a desired insulation property,. This will be described in further detail with reference to FIGS.
60
(
a
) to
62
(
c
).
FIGS.
58
(
a
) to
58
(
c
) illustrate the case of a dimensional balance in a DRAM developed before the 64-M DRAM. In this case, there is a margin in the size of the lower electrode relative to the size of the plug, so that some degree of deviation in matching causes no problem. A ruthenium film
402
is formed on the whole surface of an Si plug
401
, and a photoresist film
403
is patterned by photolithography (FIG.
58
(
a
)). Here, the photoresist film
403
is formed such that it is deviated by a distance d from an ideal patterning position (indicated by dotted lines). The ruthenium film
402
is machined by anisotropic dry-etching to form a lower electrode
404
of ruthenium (FIG.
58
(
b
)). The photoresist film
403
is removed, a dielectric film
405
is formed (FIG.
58
(
c
)), and, then, an upper ruthenium electrode is formed. Here, the size of the lower electrode
404
has a margin relative to the plug
401
. Therefore, the Si plug
401
is not exposed in machining the ruthenium film
402
to form the lower electrode
404
.
Referring to FIGS.
59
(
a
) and
59
(
b
), on the other hand, when the size of the plug becomes close to the size of the lower electrode, a deviation in matching occurs, which is a problem to be solved by this invention. The Si plug
407
is formed at a predetermined position in the insulating film
406
, and a lower ruthenium electrode
408
is formed in the same manner as in FIG.
59
(
a
). Here, the lower electrode
408
is formed such that it is deviated by a distance d from an ideal pattern position (indicated by dotted lines). The size of the lower electrode
408
is equal to the size of the plug
407
; and, hence, the Si plug
407
is partly exposed due to a deviation in matching by the distance d (portion indicated by an arrow A in FIG.
59
(
a
)). A dielectric film
409
formed in this state (FIG.
59
(
b
)) is brought into direct contact with the Si plug
407
(portion in the circle B in FIG.
59
(
b
)), and the dielectric strength of the dielectric film
409
decreases at the portion B, whereby a leakage current increases, making it no longer possible to maintain the memory function.
FIGS.
60
(
a
) to
60
(
c
) illustrate a case where a silicide film is provided to prevent a thermal reaction between ruthenium, used as the lower electrode, and the Si plug. After an Si plug
411
is formed in a predetermined region of the insulating film
410
, a silicide film
412
is formed on the surface thereof, and a ruthenium film
413
is formed on the whole surface thereof (FIG.
60
(
a
)). The ruthenium film
413
is machined by the method mentioned above to form a lower electrode
414
(FIG.
60
(
b
)). In this case, too, deviation occurs in the matching by a distance d, and the Si plug
411
is partly exposed (portion indicated by an arrow A in FIG.
60
(
b
)). That is, the silicide film
412
, too, is etched at the time of machining the ruthenium film
413
, and the Si plug
411
is partly exposed. A dielectric film
415
that is formed in this state comes into direct contact with the Si plug
411
at a portion indicated by circle B in FIG.
60
(
c
). Therefore, the leakage current inevitably increases and it becomes difficult to maintain a normal memory function.
It is therefore an object of this invention to provide a semiconductor integrated circuit device having a structure in which
Hiratani Masahiko
Iijima Shinpei
Matsui Yuichi
Nakamura Yoshitaka
Nakanishi Naruhiko
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Potter Roy
LandOfFree
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