Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-15
2003-12-09
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S246000, C438S269000
Reexamination Certificate
active
06660582
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method of forming a field-effect transistor in a semiconductor substrate. For connecting the field-effect transistor to a first conductivity region of the semiconductor substrate, a connection region to a source-drain region of the field-effect transistor is formed. For forming a potential source-drain channel path of the field-effect transistor device, an overlapping region of the source-drain region and/or of the connection region is provided with a gate insulating region.
In the case of many semiconductor circuit configurations, appropriate field-effect transistors have to be provided in a semiconductor substrate to form and connect up the underlying semiconductor circuit configuration. In particular, field-effect transistors of this type serve for connecting to a conductivity region, for example a bit line connection, an electrode connection or the like, of the semiconductor substrate, with a corresponding connection region, for example a buried-strap region, being provided for the connection of the source-drain region of the transistor to a top electrode of a storage capacitor. Furthermore, a spatial overlapping region of the source-drain region of the field-effect transistor is provided with a gate insulating region, to allow a source-drain channel path of the field-effect transistor device to be formed during operation.
The corresponding connection regions and/or the overlapping regions with the gate insulating region are usually formed as what are known as diffusion regions or diffusion contacts, with appropriate dopant material and consequently charge carriers being distributed in a thermally induced manner in the semiconductor substrate with different concentrations from a material region provided as a dopant depot.
It is problematical in this case that the underlying diffusion processes for forming the charge carrier distributions in a given material region proceed substantially isotropically. If a vertical direction of propagation is preferred, for example for contacting with vertical transistors, this results in that a lateral diffusion of the charge carriers nevertheless also takes place, with the result that under some circumstances countermeasures have to be taken to avoid undesired instances of contacting. The countermeasures have until now been realized by a greater spacing between conductivity regions or components that are to be insulated from one other. On account of this necessity to maintain minimum spacings, there are limits to the objective of highest possible component integration in an extremely small space.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method of forming a vertical field-effect transistor that overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which undesired instances of contacting of neighboring components of highly integrated circuits can be prevented in a simple way.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of forming a field-effect transistor device. The method includes providing a semiconductor substrate, forming a connection region in the semiconductor substrate, forming a conductivity region in the semiconductor substrate, and forming a source drain region. The connection region extends to the source-drain region for connecting the field-effect transistor device to the conductivity region. A potential source-drain channel path of the field-effect transistor device is formed by providing a gate insulating region to an overlapping region of the source-drain region and/or the connection region. The overlapping region is formed directly as a material region.
The method according to the invention of forming a field-effect transistor in a semiconductor substrate is characterized in that the respective overlapping region, in particular the source-drain region, of the field-effect transistor device is formed directly as a material region, in particular with lateral outdiffusion processes being avoided to the greatest extent.
Consequently, a fundamental idea of the present invention is to form and/or deposit the overlapping region of the connection region and/or of the source-drain region directly as a material. This takes place in contrast to conventional procedures, in which an overlapping region is initially formed in an electrically insulating manner, with the electrical contacting subsequently taking place indirectly, that is by outdiffusion of appropriate dopant material and consequently by subsequent introduction and distribution of corresponding charge carriers into the semiconductor region, which in itself is electrically insulating. With the direct material-based and electrically conducting contacting of the gate insulating region or gate oxide region with the connection region, the buried-strap region, or the source-drain region of the field-effect transistor, there is no longer the necessity for the subsequent distribution of charge carriers by outdiffusion, because an electrically conductive material region or a corresponding region for the electrical contacting of the gate insulating region with the remaining regions is provided directly.
In the case of a particularly preferred embodiment of the method according to the invention, the connection region and the overlapping region are formed substantially from the same material.
It is further preferred that the connection region and the overlapping region are formed substantially as one part or as one piece, whereby the process sequences can be made particularly simple and difficulties with regard to material compatibility are then avoided.
According to a further preferred embodiment of the method according to the invention, it is provided that the connection region and/or the overlapping region are grown on epitaxially and/or are formed as a single crystal, in particular as a selective epitaxial single-crystal doped silicon or the like.
According to a further embodiment of the method according to the invention, it is provided that, to avoid or suppress outdiffusion processes from the connection region and/or the overlapping region and/or to avoid or suppress undesired electrical contacts of the connection region and/or of the overlapping region with further regions, the connection region and/or the overlapping region are at least partially enclosed in an insulating region.
It is particularly advantageous if the connection region and/or the overlapping region are formed as a buried-strap structure, as a buried-strap region and/or as part thereof, in particular in a substantially buried form.
According to a further embodiment of the method according to the invention, the respective field-effect transistor device is formed as a vertical trench-structure transistor device, in particular as a deep-trench transistor or the like and/or in particular for connecting to and/or for a DRAM memory cell or the like.
For this purpose, a recess or a trench is respectively formed in the semiconductor substrate.
In an upper trench portion with upper edge regions or upper wall regions, the vertical trench-structure transistor device is formed with gate regions that are substantially electrically insulated with respect to the upper edge regions or upper wall regions and with respect to a middle trench portion to be provided.
It is further provided that, spatially adjoining the insulated gate region, substantially directly, in particular spatially beneath it, the source-drain region and the connection region are provided and formed in the region of the middle trench portion.
Furthermore, it is provided that the first conductivity region to be contacted is provided and formed substantially in a lower trench portion for forming a substantial electrical conducting contact at least with the connection region.
According to a particularly preferred embodiment of the method according to the invention, it is provided that a mask region is deposited on a surface region, which may b
Birner Albert
Goldbach Matthias
Chaudhari Chandra
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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