Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2001-12-04
2003-06-10
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C327S525000, C365S096000
Reexamination Certificate
active
06577551
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-371939, filed on Dec. 6, 2000, the entire contents of which are incorporated herein by reference.
FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit having a built-in data storage circuit for nonvolatile storage of control data.
BACKGROUND OF THE INVENTION
For years, in various semiconductor integrated circuits such as memory devices, a control data storage circuit has been formed in a chip for storing control data in a nonvolatile mode by executing programming after the wafer process. Such “control data” stored in this kind of control data storage circuits includes data for establishing the operation mode of the chip, adjustment data for adjusting the operation timing in the chip, adjusting the output voltage of the internal voltage generating circuit, and so on, chip ID information, etc. Especially, those for semiconductor memory devices include defective address judgment data for replacing a defective cell with a spare cell.
As nonvolatile memory devices of this kind of control data storage circuits, there are laser-meltdown fuses (hereinafter called laser fuses) and electrically programmable fuses (hereinafter called electric fuses). Especially, laser fuses are frequently used because of their simple structure and easy layout, but their programming is possible only before they are packaged. In contrast, electric fuses, although complicated in structure, can be programmed even after they are packaged.
Typically, data of a programmed nonvolatile memory device is read out and held in a latch circuit when the power source rises, and operative conditions of the chip will be controlled based on the data held by the latch circuit.
The above-introduced control data storage circuit has been increased in capacity along with movements of semiconductor integrated circuits toward larger scales and higher performances, and has come to include a lot of nonvolatile storage devices. Especially in semiconductor memory devices, under progressive miniaturization and movements toward larger capacities, spare rows and spare columns are prepared for enabling replacement of defective addresses to improve the production yield, and a defective address storage circuit also occupies large capacity and area.
Under the circumstances, when data of a nonvolatile storage device of the control data storage circuit is read out simultaneously with introduction of the power source, there occurs the problem that instantaneous power consumption becomes large and the peak of power consumption rises.
BRIEF SUMMARY OF THE INVENTION
According to an embodiment of the invention, there is provided a semiconductor integrated circuit comprising:
a control data storage circuit having a plurality of groups each made up of nonvolatile storage devices where control data is programmed, and a latch circuit for holding read control data from said nonvolatile storage devices; and
a read control circuit for controlling read operations of each said control data from said nonvolatile storage devices at different timings for the respective groups.
According to another embodiment of the invention, there is provided a semiconductor integrated circuit comprising:
a control data storage circuit having a plurality of groups each made up of nonvolatile storage devices where control data is programmed, and a latch circuit for holding read control data from said nonvolatile storage devices; and
first and second read control circuits each controlling read operations of said control data from said nonvolatile storage devices to take place at different timings for the respective groups.
REFERENCES:
patent: 6055197 (2000-04-01), Kato et al.
patent: 6088281 (2000-07-01), Miyakawa et al.
patent: 6118712 (2000-09-01), Park et al.
Hara Takahiko
Ito Mikihiko
Kimura Tohru
Koyanagi Masaru
Takase Satoru
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Mai Son
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