Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1999-06-09
2003-06-03
Tolin, Gerald (Department: 2835)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C257S717000, C361S719000
Reexamination Certificate
active
06574106
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a mounting structure and a method of mounting a semiconductor device, and more particularly, to a mounting structure and a method of mounting a semiconductor device in which a semiconductor device and a mounting substrate having different thermal expansion coefficients are connected to each other by connecting members.
A conventional mounting structure for a semiconductor device of this kind is, for example, a flip chip connecting structure. In flip chip connecting structure, a semiconductor device is connected to a mounting substrate with solder or conductive adhesive. More specifically, in the structure, a plurality of input/output terminals provided on the lower surface of a semiconductor device are connected with a plurality of pads provided on the upper surface of a mounting substrate, respectively, with solder or conductive adhesive.
During manufacturing, in the conventional structure such as the above-mentioned flip chip connecting structure, the solder or conductive adhesive is heated to about 200 degrees centigrade to melt the solder or to cure the conductive adhesive.
For example, when eutectic solder is used, the eutectic solder is heated to 183 degrees centigrade or higher. Heat is also applied to the semiconductor device and the mounting substrate. Because the thermal expansion coefficients of the semiconductor device and the mounting substrate are different from each other, the input/output terminals of the semiconductor device do not align with the pads of the mounting substrate after thermal expansion. When heating stops and/or cooling starts, the connecting members begin solidifying and making the input/output terminals of the semiconductor device connect to the pads of the mounting substrate, although there is a gap between positions of the input/output terminals of the semiconductor device and the pads of the mounting substrate. However, the semiconductor device and the mounting substrate contract, causing the input/output terminals and the pads to attempt to return to their original positions before the heating. This creates a problem because the connecting members are stressed when the semiconductor device, the solder, and the mounting substrate return to their ordinary temperature. When the stress exceeds the breaking stress of the connecting members, the connection between the input/output terminals and the pads breaks.
Stress produces another problem because it makes the semiconductor device and/or the mounting substrate warp or distort. In particular, when a printed substrate is used as the mounting substrate, the thermal expansion coefficient of the printed substrate is about 15×10
−6
/° C. to 20×10
−6
/° C. while that of a semiconductor device made of silicon is about 2.5 to 3.5×10
−6
/° C. Therefore, the difference between the thermal expansion coefficients of the printed substrate and of the semiconductor device is about 12 to 17×10
−6
/°C., and the stress lowers the reliability of the connection of the mounted parts. Therefore, because the difference between the thermal expansion coefficients of the printed substrate and the semiconductor device is large, stress produced to the connecting members becomes large.
In relatively small semiconductor devices the thermal expansion problem is not significant, however, as the size of the semiconductor device increases, differences between thermal expansion coefficients become a serious problem and the reliability of the devices is reduced.
Japanese Patent Application Laid-open No. Hei 8-148592 discloses a semiconductor integrated circuit device which has a semiconductor device mounted on a mounting substrate with solder bumps. The semiconductor integrated circuit device has a cap formed of a material having a thermal expansion coefficient being substantially equal to that of a semiconductor device and is secured on the upper surface of the semiconductor device. When the temperature changes due to heat generated from the semiconductor device, the semiconductor device and the cap expand and contract according to the thermal expansion coefficient of the semiconductor device. In this device, however, because the semiconductor device contracts according to the thermal expansion coefficient of the semiconductor device, the above problem of stress associated with the connecting members is not solved.
SUMMARY OF THE INVENTION
An object of the invention is to provide a mounting structure and a method of mounting a semiconductor device wherein a semiconductor device and a mounting substrate having different thermal expansion coefficients are connected to each other by connecting members, without applying stress to the connecting members.
Another object of the invention is to provide a mounting structure and a method of mounting a semiconductor device wherein reliability is improved when a semiconductor device having a large outer shape is mounted on a mounting substrate.
Another object of the invention is to provide a mounting structure and a method of mounting a semiconductor device wherein a printed substrate is used as the mounting substrate, the reliability of the connection between the printed substrate and the semiconductor device is improved.
According to one aspect of the present invention, a mounting structure for a semiconductor device is provided which includes: a substrate which has a first surface and a plurality of pads provided on the first surface; a semiconductor device which has first and second main surfaces and a plurality of terminals provided on the second main surface at locations corresponding to the pads; a plurality of connecting members which connect the pads to the terminals, respectively; and a member which has at least one surface which is coupled with the first main surface, wherein the thermal expansion coefficient of the member is equal to, or substantially equal to, that of the substrate.
According to another aspect of the present invention, a mounting structure for a semiconductor device is provided which includes: a substrate which has a first surface and a plurality of pads provided on the first surface; a semiconductor device which has first and second main surfaces and a plurality of terminals provided on the second main surface at locations corresponding to the pads; a plurality of connecting members which connect the pads with the terminals, respectively; a plate which is combined with the first main surface and has a thermal expansion coefficient being equal to, or substantially equal to, that of the substrate; and a cooling member which is thermally coupled with the plate.
According to another aspect of the present invention, a method for mounting a member and a semiconductor device on a substrate, wherein the member having at least one surface and the thermal expansion coefficient which is equal to, or substantially equal to, that of the substrate is provided which includes: coupling a surface of the member with the upper surface of the semiconductor device; positioning the semiconductor device so that terminals on a lower surface of the semiconductor device face pads on an upper surface of the substrate through connecting members, respectively; and heating the semiconductor device, the member, and the substrate to melt the connecting members, and thereafter, returning them to their ordinary temperature.
REFERENCES:
patent: 5097318 (1992-03-01), Tanaka
patent: 5396403 (1995-03-01), Patel
patent: 5621615 (1997-04-01), Dawson
patent: 5744863 (1998-04-01), Culnane et al.
patent: 5805430 (1998-09-01), Atwood
patent: 5931222 (1999-08-01), Toy
patent: 5966290 (1999-10-01), Sammakia
patent: 5969947 (1999-10-01), Johnson
patent: 5969949 (1999-10-01), Kim
patent: 6218730 (2001-04-01), Toy
patent: 0 678 917 (1995-10-01), None
patent: 5-326625 (1993-12-01), None
patent: 6-61306 (1994-03-01), None
patent: 8-148592 (1996-06-01), None
patent: 08-264688 (1996-10-01), None
patent: 9-186197 (1997-07-01), None
patent: 9-306954 (1997-11-01), None
Hasegawa et al., “Hole Grid Array
NEC Corporation
Tolin Gerald
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