Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-02
2003-06-03
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S277000
Reexamination Certificate
active
06573144
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lateral MOSFET (LDMOS) in which a source region and a drain region are arrayed in the lateral direction of a semiconductor substrate.
2. Related Arts
A power element has a structure in which several tens thousand to several hundreds thousand small LDMOSs are connected in parallel in general and these LDMOSs are operated at the same time to obtain an output.
However, there has been a problem that when a large current such as ESD (electrostatic discharge) flows through the LDMOSs instantly, the element is destroyed or wires connected to the element melt because the large current does not flow though all of the LDMOSs uniformly, but the large current concentrates on some of the LDMOSs.
Therefore, it has been required to improve a capacity for ESD surge. A high capacity for ESD surge of around 10 kV/mm
2
has been required in particular in the field of vehicular application. Although a method of adding external devices such as a capacitor to the outside of the IC chip has been adopted in the past to improve the capacity for ESD surge, such method inevitably increases the cost.
SUMMARY OF THE INVENTION
In view of the problem described above, it is an object of the invention to provide a semiconductor device whose capacity for ESD surge can be improved.
In order to achieve the above-mentioned object, the inventors have studied following points.
A non-uniformity of current at the time of ESD surge occurs due to variations of electrode resistance on a chip for example. The non-uniformity of current occurs because of a wire bonding section, that is, acurrent flow change based on a wire resistance. In concrete, a current carrying through a LDMOS near the wire bonding section flows well because the wire resistance is small. While a current carrying through a LDMOS far from the wire bonding section does not flow well because the wire resistance is large in comparison with the LDMOS near the wire bonding section.
A circuit in which an ESD surge generating circuit
50
a
shown in
FIG. 13
is connected to an LDMOS chip
50
b
in which three cells of LDMOSs
51
a,
51
b
and
51
c
are provided, i.e., a circuit in which the three cells of the LDMOSs
51
a
through
51
c
are connected to a high voltage generating circuit and resistors
52
and
53
which correspond to the resistance of wires according to a distance from a wire bonding section are disposed among the drain terminals of the respective LDMOSs
51
a
through
51
c.
When a switch
54
is turned ON, power is supplied from a high voltage power source
55
and a capacitor
56
is charged in the surge generating circuit
50
a.
Then, when a switch
57
is turned ON after turning OFF the switch
54
, an ESD surge current flows through the three cells of the LDMOSs
51
a
through
51
c,
respectively. Since an L load
58
is included within the circuit, a large current caused by the ESD surge current flows through the three cells of the LDMOSs
51
a
through
51
c
at this time.
Then, when the inventors conducted a simulation analysis with such circuit, drain currents Id
1
, ID
2
and Id
3
of the respective MOSFET
51
a
through
51
c
and drain voltages Vd
1
, Vd
2
and Vd
3
of the respective MOSFET
51
a
through
51
c
were represented as shown in FIG.
14
.
As it is apparent from this chart, although the drain current Id
1
flowing through the LDMOS
51
a
directly connected with the power supply line suddenly increases from the start of a concentration of current, the drain currents Id
2
and Id
3
flowing through the LDMOSs
51
b
and
51
c
connected to the power supply line via the resistors
52
and
53
decrease.
It is because a current-voltage characteristics of the LDMOS has a negative resistance. Namely, the current flowing through the LDMOS
51
a
comes into values on a negative resistance region so that a positive feedback occurs and a drain voltage drops when the concentration of current starts as indicated by the upward arrow in the in
FIG. 15
, while currents flowing through each of the LDMOSs
51
b
and
51
c
does not come into the values on the negative resistance region, thereby dropping the currents flowing through the LDMOSs
51
b
and
51
c
with drop of each drain voltage as indicated by a downward arrow in FIG.
15
.
The negative resistance occurs when a voltage between a source and a drain decreases although the drain current is still increasing. This voltage drop occurs due to the fact that a width of the depletion layer at a PN junction does not vary although the drain current is still increasing.
That is, although the voltage between the source and the drain corresponds to an integral value of electric field strength between the source and the drain, the voltage between the source and the drain is decreased because the field strength drops when the drain current becomes a large current. As a result, the negative resistance occurs.
The inventors obtained results shown in
FIGS. 16A and 16B
by simulating changes of a distribution of field strength under two different conditions, i.e., the drain current is
20
A and the drain current is
200
A. The field strength at a part A-A′ in
FIGS. 16A and 16B
is shown in FIG.
17
. It also can be seen from the result that the voltage between the source and the drain, which corresponds to the integral value (area) of the field strength between the source and the drain, decreases when the drain current increases, thus causing the negative resistance.
As described above, the LDMOS has the negative resistance shown in FIG.
15
. As a resistance of the LDMOS
51
a
is inside of the negative resistance region, a current flowing through the LDMOS
51
a
increases with a decrease of voltage applied between a source and a drain of the LDMOS
5
l
a.
However, resistance between a source region and a drain region in each of the LDMOSs
51
b
and
51
c
is outside of the negative resistance region, so that the current applied to each of the LDMOSs
51
b
and
51
c
decreases.
Therefore, the ESD surge current concentrates on the LDMOS
51
a,
thus destroying the element of the LDMOS
51
a
or melting a wire connected with the LDMOS
51
a.
After all, it is possible to prevent the local concentration of the ESD surge current and to improve the capacity for ESD surge by improving the negative resistance described above. The inventors studied about the improvement of the negative resistance.
The negative resistance occurs while the drain current is still increasing although a width of the depletion layer at a PN junction does not vary as described above. Accordingly, the inventors considered that the negative resistance may be improved by modifying a structure by which the width of the depletion layer formed at the PN junction may is acquired, i.e., by modifying a structure in which the depletion layer hardly extends in the vicinity of the drain region.
Then, as a result of trials and errors, the inventors devised an LDMOS shown in
FIG. 18
as the structure satisfying the above conditions.
The LDMOS has a structure in which a drain region is surrounded by an n-type region
6
. An impurity concentration in the n-type region
6
is set so that the impurity concentration gradually increases from a semiconductor layer
1
to the drain region
5
. In other words, the closer to the drain region
5
centering on the drain region
5
, the denser the concentration of n-type impurity concentration in the n-type region
6
becomes.
The inventors conducted a simulation analysis to simulate how the negative resistance changes by changing the impurity concentration in the n-type region
6
, or more concretely an impurity concentration in a surface part of the n-type region
6
(hereinafter referred to as a surface concentration).
FIG. 19
shows a result. It is noted that the above-mentioned analysis was carried out by the simulation under a diffusion condition that the surface concentration in then-type region
6
is changed within a hatched range in FIG.
20
. More specifically, the analysis was
Himi Hiroaki
Kato Masatoshi
Shiraki Satoshi
Takahashi Shigeki
LandOfFree
Method for manufacturing a semiconductor device having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing a semiconductor device having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a semiconductor device having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3130735