Hybrid open folded sense amplifier architecture for a memory dev

Details Hybrid open folded sense amplifier architecture for a memory dev Hybrid open folded sense amplifier architecture for a memory dev

1991-12-12

1994-01-04

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Multiplexing

365207, G11C 1300

Patent

active

052766411

ABSTRACT:
A hybrid open/folded bit line sense amplifier arrangement and accompanying circuitry primarily for use on a ULSI DRAM memory chip to reduce the area needed for a memory cell and eliminate noise between bit lines. The circuitry includes two memory arrays containing a plurality of memory cells interconnected by a plurality of bit lines and word lines. In the preferred embodiment, the memory cells are accessible on every two out of three bit lines encountered by a word line. A set of open bit line sense amplifiers each with two connectors, one multiplexed to a number of bit lines in the first array and the other multiplexed to a number of bit lines in the second array is provided. Each memory array has a set of folded bit line sense amplifiers with two connectors each connector multiplexed to a number of bit lines in the array. The control circuitry with multiplexing ensures that the connectors of the sense amplifiers access only one bit lines at a time. The accessed by the connectors of each folded line sense amplifier are non-adjacent and simultaneously therewith, a connector of an open bit sense amplifier accesses a bit line between the bit lines accessed by the folded sense amplifier. In the preferred embodiment each connector of a sense amplifier is multiplexed to three bit lines. In a second version the connectors are multiplexed to two bit lines.

REFERENCES:
patent: 4586171 (1986-04-01), Fujishima
patent: 4700328 (1987-10-01), Burghard
patent: 4733374 (1988-03-01), Furuyama et al.
patent: 4916661 (1990-04-01), Nawaki et al.
Saeki, T. et al, "A Study of Close Packed Folded Bit-Line Cell Array (CPF) and Three Phase Folded Bit-Line Array / Circuit (TPF) for DRAM's", Nikkei Micro Devices, May 1991.

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