Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-19
2003-12-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000
Reexamination Certificate
active
06656799
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device in which a source/drain region occupies a reduced area so as to decrease the parasitic capacitance and parasitic resistance of the source/drain region, as well as a method for producing the same.
2. Description of the Related Art
In general, smaller insulation gate type field effect transistors (FETs) become more susceptible to problems such as fluctuation in the threshold voltage due to variation in the gate length caused by processing variations, an increased off-leak current due to deterioration of subthreshold characteristics, and deterioration of transistor characteristics due to short channel effects, e.g., so-called punch-through.
One method for solving such problems has been to reduce the junction depth of the source/drain regions adjoining a channel region of a transistor. A reduced junction depth can be realized by, for example, a structure in which source/drain regions (stacked diffusion layers) are stacked on both sides of a gate electrode so as to be located above the-channel region via gate electrode lateral wall insulation films.
FIGS. 22A
,
22
B, and
22
C are cross-sectional views illustrating-steps of a conventional method for forming stacked diffusion layers.
As shown in
FIG. 22A
, a gate electrode
1005
whose upper face and side walls are covered with an insulation film
1006
is formed upon a semiconductor wafer
1001
, with a gate insulation film
1004
interposed therebetween. The semiconductor wafer
1001
generally includes an active region
1003
(composed of a silicon substrate) and device separation regions
1002
(composed of a silicon oxide film).
Next, as shown in
FIG. 22B
, a selective epitaxial growth method is used to grow a silicon film
1007
exclusively in regions (source/drain regions) where the silicon surface is exposed, thereby forming stacked diffusion layer regions (which are composed of a semiconductor) in the source/drain regions. A selective epitaxial growth method is disclosed in Japanese Laid-open Publication No. 61-196577.
As shown in
FIG. 22C
, an interlayer insulation film
1008
is formed, and upper wiring
1010
is coupled to the source/drain regions
1007
via contact wires
1009
.
After the silicon film (epitaxial silicon, polycrystalline silicon, etc.) has been formed above the channel region, impurity ions are implanted so as to form the source/drain regions. By thus implanting impurity ions in the stacked silicon films which are located above the channel region, it becomes possible to reduce the junction depth of the source/drain region impurity diffusion layers relative to the channel region of the transistor. As a result, so-called short channel effects can be effectively prevented.
The source/drain regions
1007
extend from the gate electrode
1005
to the device separation regions
1002
along a direction X-X′ (commonly referred to as the “gate length direction”) which is perpendicular to the longitudinal direction of the gate electrode. When contact holes are formed in such source/drain regions
1007
, the length of each source/drain region
1007
will be determined as follows.
FIG. 15
is a diagram illustrating the relationship between a gate electrode, an active region, and contact holes. A positioning margin p is provided between the gate electrode and each contact hole. Each contact hole has a width o. The contact holes are positioned with respect to the source/drain regions with a margin q as illustrated in FIG.
15
. It will be appreciated that the length of each source/drain region
1007
cannot become smaller than p+o+q in the semiconductor device illustrated in FIG.
22
C.
Thus, it is difficult to reduce the area occupied by the source/drain regions in accordance with the semiconductor device disclosed in Japanese Laid-open Publication No. 61-196577.
SUMMARY OF THE INVENTION
A semiconductor device having a device separation region and an active region according to the present invention includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region, wherein the active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face; and wherein the electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.
In one embodiment of the invention, the second face is substantially rugged.
In another embodiment of the invention, a portion of the source/drain region partially covers the device separation region.
In still another embodiment of the invention, the height of the source/drain region as measured from the first face along a direction perpendicular to the first face increases toward the gate electrode.
In still another embodiment of the invention, the second face has a curved profile.
In still another embodiment of the invention, a portion of a contact hole for interconnecting the source/drain region and upper wiring is present on the surface of the source/drain region.
In still another embodiment of the invention, a distance between an end of the gate electrode and an end of the contact hole that is located away from the gate electrode in a cross section extending along a direction perpendicular to a longitudinal direction of the gate electrode and through a center of the contact hole is larger than a distance between the end of the gate electrode and an interface between the active region and the device separation region.
In still another embodiment of the invention, a width of the contact hole as measured in a cross section extending along a direction perpendicular to a longitudinal direction of the gate electrode and through a center of the contact hole is larger than a distance between an end of the gate electrode and an interface between the active region and the device separation region.
In still another embodiment of the invention, in a cross section extending along a direction perpendicular to a longitudinal direction of the gate electrode, a distance between an end of the gate electrode and an interface between the active region and the device separation region is smaller than a width of the gate electrode, the width of the gate electrode defining a gate length of the semiconductor device.
In still another embodiment of the invention, a diffusion coefficient of an impurity within a stacked layer constituting the source/drain region is larger than a diffusion coefficient of an impurity within the semiconductor substrate.
In still another embodiment of the invention, the diffusion coefficient of the impurity within the stacked layer is about 2 to about 100 times as large as the diffusion coefficient of an impurity within the semiconductor substrate.
In still another embodiment of the invention, the stacked layer includes polycrystalline silicon.
In still another embodiment of the invention, the polycrystalline silicon includes columnar crystals.
In still another embodiment of the invention, the polycrystalline silicon has a grain size of about 50 nm or less.
In still another embodiment of the invention, a surface of the gate electrode and the source/drain region is covered by a two-layer film, the two-layer film including a polycrystalline silicon film and a refractory metal silicide film.
In still another embodiment of the invention, a junction depth of the source/drain region from the first face is about 0.8 to about 2 times as large as a width of the gate electrode lateral wall insulation film.
In another aspect of the invention, there is provided a method for producing a semiconductor device having a device separation region and an active region, the method including the steps of: forming the device separation region on a silicon substrate from a material which substantially withstands silicon etching; sequentially forming a gate insulation film, a gate electrode, and a gate electrod
Adachi Kouichiro
Iwata Hiroshi
Kakimoto Seizo
Nakano Masayuki
Fourson George
Pham Thanh V
Sharp Kabushiki Kaisha
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