Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-07-13
2003-10-21
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000, C716S030000
Reexamination Certificate
active
06636995
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the testing of logic circuits in integrated circuit devices and, in particular, to a method of automatic latch insertion for testing application specific integrated circuits (ASICs).
2. Description of Related Art
As application specific integrated circuit (ASIC) designs grow in complexity, the overhead for manufacturing testing grows as a result of the larger test pattern set required for complete 100% test coverage. Test pattern coverage to the 100% level requires a large test time because of the number of test patterns required. In prior designs, test coverage analysis has been limited to modification of the design manually to bring coverage up to near 100%. No automated process exists which looks at a part that has achieved a test coverage goal, to optimize the pattern set length to reduce test time, while simultaneously maintaining the design's objectives for circuit area and logic performance.
Prior art in this area includes U.S. Pat. Nos. 5,502,731; 5,544,173; 5,661,733; 5,719,878 and 5,748,647, and JP01-196159A.
There exist tools in the industry that are capable of determining and even inserting control and observe test point in a netlist. However, these solutions are an additional, often iterative step in the design process. In such solutions, the test points are assessed and inserted. The design must then be assessed for new area, timing, and other design objectives in the tools that have these capacities, such as synthesis, timing analysis, and the like. Test points that violate the design criteria must then be removed from the list, and the insertion process repeated. This entire sequence is then reiterated until a set of test points are inserted that satisfy the timing, area and other criteria. A flow diagram depicting this prior art testing method is shown in FIG.
1
. As a result, a general problem exists as to how to minimize test, design costs and overhead for integrated ASIC subsystems.
Although the shrinking dimensions of integrated circuits are lowering the costs of the silicon manufacture on a per die basis, the test costs are not being similarly reduced. Test times for ASIC subsystems are actually growing, causing manufacturing test to become a larger portion of the cost of the completed ASIC. There is a need for reducing test times, without impacting the design constraints of performance and area, while maintaining complete test coverage. Additionally, any such solution needs to be extendible such that it does not impact the added design constraints in effectively utilizing the performance and density advantages of shrinking process geometries and improved interconnect processes. Such constraints include interconnect parasitics and wire congestion. Finally, the solution cannot impact the ASIC development schedule. Design methods to maintain complete test coverage must be fully integrated with the design of the ASIC's function.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved method of testing ASICs.
It is another object of the present invention to provide a method of testing ASICs which reduces test times, without impacting the design constraints of performance and area, and maintaining complete test coverage.
A further object of the invention is to provide a method of testing ASICs which does not impact any added design constraints.
It is yet another object of the present invention to provide a method of testing ASICs which maintain complete test coverage while being fully integrated with the design of the ASIC's function.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
SUMMARY OF THE INVENTION
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of testing a digital logic circuit comprising first a logic circuit having a plurality of interconnected circuits each having an input and an output; determining a gate level representation of the logic circuit including test nets for determining faults in the circuit; and identifying a portion of the nets which are most difficult to test, including nets which are most difficult to control and nets which are most difficult to observe. The method then includes inserting into the logic circuit control latches for nets which are determined to be most difficult to control and inserting into the logic circuit observation latches for nets which are determined to be most difficult to observe. Using the inserted control latches and observation latches, the method further includes testing the nets which are determined to be most difficult to control and nets which are hardest to observe and determining faults in the circuit. As a result of the method of the present invention, testing is completed in a time faster than if the nets were tested without the control latches and the observation latches. The portion of the nets which are most difficult to test are preferably identified by overall test time impact, and the nets having longest test times are determined to be most difficult to control and most difficult to observe.
In one embodiment of the present invention, the method includes tracing the logic network of the logic circuit and determining for each net a score of: i) distance in logic levels from a source latch; ii) distance in logic levels from a destination latch; iii) logic cone size that generates the net; and iv) number of latches fed by the cone driven by the net. The control and observation latches are then inserted for those nets which have qualitative scores which differ most from predetermined scores.
In another embodiment of the present invention, the method includes using a test diagnosis tool to determine test patterns, determining faults covered by each test pattern, and for each net the number of vectors needed before the net was tested. The control and observation latches are then inserted for those nets which are either determined to be not testable or which have the most vectors applied before the net was tested.
In another embodiment of the present invention, the method includes, prior to inserting the observation latches into the logic circuit, the logic cone that generates the nets is broken into at least two pieces and the observation latches and/or control latches are inserted. The method then includes, for each piece of the logic cone, calculating new design area and new timing slack for logic paths having the inserted control latches and observation latches. If the new design area and new timing slack for logic paths having the inserted control latches and observation latches violate predetermined limits, the inserted control latches are removed from the logic circuit, leaving only observation latches.
Testing of the nets preferably includes calculating new design area and new timing slack for logic paths having the inserted control latches and observation latches. The inserted control latches and observation latches remain in the logic circuit if the new design area and new timing slack for logic paths having the inserted control latches and observation latches do not violate predetermined limits. The inserted control latches and observation latches are removed from the logic circuit if the new design area and new timing slack for logic paths having the inserted control latches and observation latches violate predetermined limits.
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Dean Alvar A.
Iadanza Joseph A.
Lackey David E.
Ventrone Sebastian T.
Curcio Robert
DeLio & Peterson LLC
International Business Machines - Corporation
Tu Christine T.
Walsh Robert A.
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