Method of forming a uniform ultra-thin gate oxide layer

Details Method of forming a uniform ultra-thin gate oxide layer Method of forming a uniform ultra-thin gate oxide layer

2001-09-17

2003-08-05

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

By reaction with substrate

C438S770000

Reexamination Certificate

active

06602799

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally related to forming insulating oxide layers over semiconductor device structures, and more particularly, to a method of forming a highly uniform ultra-thin insulating gate oxide layer on a silicon wafer.
BACKGROUND OF THE INVENTION
In the semiconductor fabrication process, one of the more important processing steps is the formation of a high quality insulating gate oxide layer in the field of semiconductor devices fabrication. Many broad categories of commercial devices, such as electrically erasable programmable read only memories (EEPROMs), dynamic random access memories (DRAMs), and more recently, even high-speed basic logic functions, owe their commercialization to the reproducibility of high quality, very thin oxide layers. High quality dielectrics are needed in such devices to achieve satisfactory device performance both in terms of speed and longevity.
As in many aspects of semiconductor processing, current scaling efforts involve a set of trade-offs between higher packing density and better performance, and short channel effects. As process technologies scaled below about 2.0 microns, a series of design difficulties arose stemming from the semiconductor physics associated with short-channel devices. Hot carrier effects and sub-threshold leakage currents become much more problematic in short channel devices.
One technique to combat short channel effects has involved the scaling of gate dielectrics. To compensate for the potentially lower drive currents for a given short channel device, conventional silicon dioxide gate oxide layers are made as thin as possible to maximize drive current. However, the scaling of silicon dioxide gate dielectric layers has introduced another set of problems. To begin with, very thin silicon dioxide layers have been historically difficult to fabricate with a consistent thickness across a given wafer, from wafer to wafer and from lot to lot. In addition, as the thickness of silicon dioxide is scaled downward, the potential for reliability problems associated with dielectric breakdown and hot and cold carrier injection degradation increases. Hot and cold carrier degradation can significantly reduce device performance, while dielectric breakdown can lead to complete device failure.
Ultra-thin gate oxides (less than 3 nm) are required for achieving small/fast device technology. Uniformity is one of the major challenges in ultra-thin gate oxide fabrication since such uniformity is strongly correlated with gate oxide integrity. Present gate insulating layers fall short of the requirements necessary for future devices. Most conventional gate insulating layers are pure SiO
2
(silicon dioxide) films formed by thermal oxidation. Others employ a combination of a high temperature deposited SiO
2
layer on a thermally grown layer.
Generally, silicon dioxide layers can be grown within a temperature range from about 400° C. to about 1150° C. The growth process may be carried out in resistance-heated furnaces or in rapid thermal process chambers with heat provided by, for example, tungsten-halogen lamps. Typically, either a horizontal or a vertical furnace tube is used for this purpose. After loading a batch of wafers into a furnace, the furnace is heated to (ramped-up) a temperature suitable for oxidation of silicon. According to the prior art, wafers are then held at the elevated temperature (annealed) for a period of time to grow an oxide layer and then cooled (ramped-down) to a lower temperature.
During the oxidation process, as wafers are heated in the furnaces, a temperature profile within the furnace develops whereby the temperature at the wafer edge is higher than at the wafer center, leading to non-uniformity in oxide layer growth. The non-uniformity of the temperature profile and therefore the oxide layer uniformity increases as wafer size increases (e.g., from 200 mm to 300 mm). Further, the effects of such oxide layer non-uniformity become intolerable as oxide layer thickness is scaled down to the direct tunneling regime (e.g., less than 3 nm).
Silicon dioxide (SiO
2
) can be grown by either a dry oxidation process or a wet oxidation process. In a dry oxidation process, oxygen is mixed with an inert carrier gas such as nitrogen, and is passed over a batch of process wafers at an elevated temperature. In a wet oxidation process, the process can be carried out by bubbling oxygen through high purity water maintained at a temperature of about 90° C. The temperature of the water determines the partial pressure of water vapor in the oxygen gas stream. The water vapor/oxygen gas mixture is then passed over the process wafers at a predetermined elevated temperature. The wet oxidation process may also be carried out in a pyrogenic steam oxidation process in which the oxidizing medium is water vapor formed by direct reaction between hydrogen and oxygen.
FIG. 1
shows a typical pyrogenic steam oxidation apparatus (
10
) according to the prior art. As shown in
FIG. 1
, a pyrogenic steam oxidation process may be carried out in horizontal furnace tube (
12
) situated in furnace (
14
). Inside the furnace tube (
12
), a wafer bolt (
16
) is used to hold a batch of silicon wafers (
20
) in an upright position. Oxygen gas (
22
) is fed into furnace tube (
12
) by carrier inert gas (e.g., nitrogen) (
24
) through inlet (
30
). Water vapor is thus formed by direct reaction between hydrogen and oxygen in furnace tube (
12
) acting as an oxidizing medium to produce SiO
2
on the silicon wafers (
20
). Unused water vapor and reaction by-products are passed out of furnace tube (
12
) through outlet (
32
).
The thermal budget required to achieve a given oxide film thickness is considerably smaller in a wet oxidation process compared to a dry oxidation process, making the wet oxidation preferable in many instances. However, the smallest fabricated dimension in a semiconductor device is frequently the gate-oxide thickness and the process control of a pyrogenic steam oxidation process proves more difficult compared to a dry oxidation process.
For example, in a 0.35 micron device, a 70 Angstrom gate oxide thickness must be controlled to within 7 Angstroms in order to meet stringent Industry reliability requirements. These requirements, for example, translate into a defect density of less than 0.5/cm3.
A process for growing such ultra-thin oxide layers therefore requires careful process control and furnace optimization. As the diameter of silicon wafers becomes larger, e.g., increased from 150 mm to 200 mm or 300 mm, larger furnace tubes must be utilized which further complicates the ambient control process. Furthermore, as device dimensions are further reduced below the 0.25 micron level, the thickness of the gate oxide layers will be likewise be reduced in scale to about 50 Angstroms.
Controlling the growth of an ultra-thin oxide layer of 50 Angstroms is difficult to control according to the steam oxidation process of the prior art shown in FIG.
1
. One reason for such difficulty is simply the short pyro-time required for depositing such ultra-thin oxide layers. Another reason is the high annealing temperatures required to treat such ultra-thin oxide layers to obtain a high quality oxide. The annealing process for the ultra-thin oxide layers typically requires temperatures of about 1000° C. At this temperature, any residual moisture in the reaction chamber or in conduits leading to the reaction chamber may be a source of oxygen and cause unexpected further oxide growth on the wafers thereby leading to an unpredictable thickness of the oxide layer.
The process control difficulty according to the prior art is more clearly demonstrated in FIG.
2
. Here, oxide thickness deposited on processed wafers in a vertically oriented furnace is shown versus time over a two-month period. Oxide thickness of wafers situated in an upper, central, and lower portion of the furnace are represented at (
22
). In
FIG. 2
, however, the variations in thickness are dominated by variations between oxidation runs. As demonstrated in
FIG

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