Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2001-12-03
2003-11-18
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S780000, C257S781000, C257S784000, C257S773000, C257S690000, C257S758000, C257S774000, C438S618000, C438S666000
Reexamination Certificate
active
06650021
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a recessed bond pad within an electronic device, and an associated method of fabrication.
2. Related Art
An electronic device, such as a semiconductor chip, typically has a bond pad on its exterior surface for placement of a conductive interconnect, such as a wirebond. A force applied to the wirebond in the direction of the bond pad ensures that the wirebond makes a reliable connection with the bond pad. Such force to the wirebond propagates into the electronic device and such force must consequently be withstood by material structures within the electronic device below the wirebond, including dielectric structures within the electronic device.
With successive generations of electronic devices, wiring density within electronic devices has been increasing. The increased wiring density, and consequent shorter distances between conductive wires, unfortunately leads to increased undesired capacitance between, and within, wiring levels for given dielectric materials between the conductive wires. A method of preventing the aforementioned decrease in undesired capacitance includes using dielectric materials having lower dielectric constants to an extent necessary to compensate for the reduced spacing between conductive wires. Candidate materials having lower dielectric constants, however, tend to be more porous, and thus mechanically weaker, than mechanically stronger dielectric materials currently being used in electronic devices. Unfortunately, such mechanically weak dielectric materials are unable to withstand the aforementioned forces applied to wire pads during wirebond, testing, or solder bumping and are thus not viable candidates for reducing capacitance so long as they are must bear the forces applied to wirebonds or test probes.
A method is needed for enabling mechanically weak dielectric materials having low dielectric constants to be utilized in an electronic device coupled to a wirebond or test probes, such that forces applied to the wire pads are not transmitted to the mechanically weak dielectric materials.
SUMMARY OF THE INVENTION
The present invention provides an electronic device, comprising:
a substrate;
a system of N contiguous levels of interconnect metallurgy on the substrate, wherein each level is formed at a different elevation above the substrate, wherein level N is coupled to the substrate, and wherein N is a positive integer of at least 3;
a first group of metallic etch stops at level M, wherein M is an integer no less than 3 and no greater than N;
a second group of metallic etch stops at level M−1, wherein the second group of metallic etch stops conductively contacts the first group of metallic etch stops in an overlapping multilevel matrix pattern;
a cylindrical space that encompasses:
levels
1
,
2
, . . . , M−1 above the first group of metallic etch stops, and levels
1
,
2
, . . . , M−2 above the second group of metallic etch stops; and
a bond pad within the first cylindrical space, wherein the bond pad is substantially formed at level K, wherein K is a positive integer of at least 1 and no greater than M−2, wherein the bond pad is conductively coupled to both the first group of metallic etch stops and the second group of metallic etch stops, and wherein the bond pad includes a surface having an exposed portion.
The present invention provides an electronic device, comprising:
a substrate;
a system of N contiguous levels of interconnect metallurgy on the substrate, wherein each level is formed at a different elevation above the substrate, wherein level N is coupled to the substrate, and wherein N is a positive integer of at least 2;
a group of metallic etch stops at level M, wherein M is an integer no less than 2 and no greater than N;
a cylindrical space that encompasses levels
1
,
2
, . . . , M−1 above the group of metallic etch stops; and
a bond pad within the cylindrical space, wherein the bond pad is substantially formed at level K, wherein K is a positive integer of at least 1 and no greater than M−1, wherein the bond pad is conductively coupled to the group of metallic etch stops, and wherein the bond pad includes a surface having an exposed portion.
The present invention provides an electronic device, comprising:
a substrate;
a system of N contiguous levels of interconnect metallurgy for interconnecting semiconductor devices, wherein the system is on the substrate such that level N is coupled to the substrate, wherein N is a positive integer of at least 2, and wherein each level is formed at a different elevation above the substrate;
a plurality of bond pads coupled to the system, wherein at least one of said bond pads is substantially formed at level M, and wherein M is a positive integer less than N.
The present invention provides a method for forming an electronic device having a recessed bond pad, comprising the steps of:
providing a substrate and a system of N contiguous levels of interconnect metallurgy on the substrate,
wherein each level is formed at a different elevation above the substrate,
wherein N is a positive integer of at least 3,
wherein level N is coupled to the substrate,
wherein a first group of metallic etch stops is formed at level M,
wherein M is an integer no less than 3 and no greater than N,
wherein a second group of metallic etch stops is formed at level M−1,
wherein the second group of metallic etch stops conductively contacts the first group of metallic etch stops in an overlapping multilevel matrix pattern,
wherein a metal pad is formed at level K,
wherein K is a positive integer of at least 1 and no greater than M−2,
wherein a cylindrical space encompasses levels
1
,
2
, . . . , M−1 above the first group of metallic etch stops, and levels
1
,
2
, . . . , M−2 above the second group of metallic etch stops, and
wherein the cylindrical space includes dielectric material and encloses the metal pad,
etching away the dielectric material in the cylindrical space, leaving a void that supplants the etched dielectric material, leaving exposed surfaces of the cylindrical space, and leaving the metal pad exposed; and
forming a conductive layer around the exposed metal pad, wherein the conductive layer includes a conductive metal, and wherein the bond pad includes the conductive layer and the metal pad.
The present invention has the advantage of enabling mechanically weak dielectric materials having low dielectric constants to be utilized in an electronic device coupled to a wirebond, such that forces applied to the wirebonds are not transmitted to the mechanically weak dielectric materials.
The present invention has the advantage of utilizing an overlapping multilevel matrix pattern of metallic etch stops, which enables the dimensions of individual etch stops to be limited. It is desirable to limit the width of the individual etch steps to a single width because the photolithography, reactive ion etching (RIE), metal fill, and subsequent processes can be optimized for a single line width.
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patent: 5783868 (1998-07-01), Galloway
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patent: 6297563 (2001-10-01), Yamaha
patent: 6313537 (2001-11-01), Lee et al.
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patent: 6420254 (2002-07-01), Stamper et al.
patent: 6522021 (2003-02-01), Sakihama et al.
Elimination of Bond-pad Damage Through Structural Reinforcement of Intermetal Dielectrics, Saran et al., Mar. 31, 1998, pp. 225-231.
Stamper Anthony K.
Yankee Sally J.
Loke Steven
Parekh Nitin
Sabo William D.
Schmeiser Olsen & Watts
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