Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-28
2003-02-25
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C257S327000
Reexamination Certificate
active
06524903
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing technique of a semiconductor device, particularly to a technique effective when applied to a semiconductor device having a MISFET (metal insulator semiconductor field effect transistor) of the generation of a gate length not greater than 0.1 &mgr;m.
As a MISFET capable of controlling short channel effects, a MISFET having a punch through stopper layer of a pocket structure is described in Japanese Patent Application Laid-Open No. Hei 4(1992)-58562.
This MISFET is fabricated by ion-implanting a second conductivity type impurity to the surface of a substrate with a gate electrode, which has been formed over a first conductivity type substrate through an insulating film, as a mask, thereby forming a first diffusion region; ion-implanting a first conductivity type impurity below this first diffusion region, thereby forming a second diffusion region, that is, a so-called punch-through stopper layer having a pocket structure; forming a conductive side wall film on both sides of the gate electrode; and then ion-implanting a second conductivity type impurity into the surface of the substrate with the side wall film and the gate electrode as a mask, thereby forming a third diffusion region.
The short channel effects occur mainly because an electric field generated from the drain of a MISFET reaches the source, thereby causing an electric current to flow between the source and drain. In the above-described MISFET, however, the electric field intensity generated from the drain is suppressed by the punch-through stopper layer (second diffusion region) having a reversal field type pocket structure, making it possible to avoid generation of short channel effects even if the gate length is 0.2 &mgr;m or so.
SUMMARY OF THE INVENTION
As a result of investigation of a MISFET having a punch-through stopper layer of a pocket structure, however, the present inventors found the below-described problems.
Miniaturization of a gate electrode of a MISFET in the width direction of a source or drain (hereinafter called “gate length” simply) is necessary for high integration of a semiconductor device. In a MISFET having a gate length not greater than 0.1 &mgr;m, when the punch-through stopper layer of a pocket structure has an extension of 0.03 &mgr;m or greater, this extension below the gate electrode accounts for at least 60% of the gate length. Owing to variations in the shape of a gate electrode or in an ion-implantation angle upon formation of a punch-through stopper layer, fluctuations of a threshold voltage of a MISFET therefore occur.
An object of the present invention is therefore to provide a technique capable of suppressing fluctuations in the threshold voltage and improving a switching rate in a short channel MISFET.
The above and other objects and novel features of the present invention will become apparent from the following description therein and accompanying drawings.
Among the inventions disclosed in the present application, typical ones will be summarized briefly as follows.
In the present invention, there are provided a semiconductor device and its manufacturing method comprising, upon formation of a MISFET having a gate length not greater than about 0.1 &mgr;m, forming a first conductivity type impurity layer having a first peak in impurity concentration distribution and another first conductivity type impurity layer having a second peak in impurity concentration distribution in a substrate; forming source and drain extension regions of a second conductivity type in the substrate after formation of a gate electrode; and forming source and drain diffusion regions of the second conductivity type in the substrate after formation of side wall spacer on the side walls of the gate electrode;
wherein the first peak exists in a region shallower than the joint depth of the source and drain diffusion regions; and the second peak exists in a region deeper than a channel region. In another aspect, the impurity concentration of the second peak is greater than that of the first peak. In a further aspect, the sum of the impurity concentrations of the channel region is 5×10
17
/cm
3
or less. In a still further aspect, as an element for constituting an impurity layer of the second peak, that having a greater mass than the mass of an element constituting the impurity layer of the first peak is ion implanted.
According to the above-described means, by forming an impurity layer having a function of preventing punch-through all over the surface of the substrate below the channel region of a MISFET, fluctuations of a threshold voltage can be suppressed compared with the case where a punch-through stopper layer is formed by a pocket structure. In addition, the controllable width of a depletion layer becomes relatively large by imparting two peaks, that is, first peak and second peak, to impurity concentration distribution of the impurity layer, making it possible to decrease a sub-threshold swing. This prevents lowering of a threshold voltage and improving a switching rate of a MISFET. Moreover, since the sum of the impurity concentrations of the channel region is not greater than 5×10
17
/cm
3
, mobility can be heightened. As an element for constituting an impurity layer of the second peak, that having a greater mass than the mass of an element constituting the impurity layer of the first peak is ion implanted so that the surface concentration can be decreased while heightening a peak concentration, making it possible to prevent lowering of mobility. In addition, an on-state current can be improved at a drain voltage of 1V or less compared with a pocket structure. In other words, in the MISFET of the present invention, an on-state current can be improved by operation at a supply voltage of 1V or less.
REFERENCES:
patent: 5719081 (1998-02-01), Racanelli et al.
patent: 5827763 (1998-10-01), Gardner et al.
patent: 6153454 (2000-11-01), Krivokapic
patent: 6342429 (2002-01-01), Puchner et al.
patent: 6365473 (2002-04-01), Lee
Ohnishi Kazuhiro
Onai Takahiro
Ootsuka Fumio
Wakahara Shoji
Antonelli Terry Stout & Kraus LLP
Cao Phat X.
Le Thao X.
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