Trace control circuit adapted for high-speed microcomputer...

Details Trace control circuit adapted for high-speed microcomputer... Trace control circuit adapted for high-speed microcomputer...

2000-06-07

2003-10-14

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C714S045000

Reexamination Certificate

active

06633973

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a trace control circuit constituting a part of a debugging circuit built into a microcomputer.
2. Description of the Related Art
Generally speaking, an in-circuit emulator (ICE) is used for program debugging in a microcomputer. The function of an ICE is to emulate the function of the microcomputer subject to program debugging. An address bus and a data bus of the microcomputer are connected to a memory on the ICE. A host computer controlling the ICE downloads a program executed by the microcomputer to the memory on the ICE so that the microcomputer is operated.
In an LSI having a built-in microcomputer, the program is usually stored in a memory provided in the microcomputer. For this reason, the address bus and the data bus for connection with the memory on the ICE are not provided in the terminals of the LSI.
Therefore, a mode dedicated to connection to the ICE is provided. In this mode, the address bus and the data bus are connected to the memory on the ICE by leading the address bus and the data bus to external terminals of the LSI, so that emulation using the ICE is enabled.
However, since the connection between the ICE and the system LSI requires as many connections as the number of terminals in the microcomputer, connection between the ICE and the system LSI involves difficulties as the speed of the microcomputer and the number of buses are increased. It is to be noted further that various functions for system implementation other microcomputer functions are built into the system LSI with a built-in microcomputer. It is thus difficult to perform emulation of the function of the external terminals of the LSI to which the address bus and the data bus are led for connection with the memory on the ICE.
In this background, recently, a debugging circuit complementing the ICE function is built into the microcomputer and connected to an external debugger via LSI terminals dedicated to debugging.
FIG. 7
is a block diagram showing a related-art microcomputer. Referring to
FIG. 7
, numeral
1
indicates a microcomputer having a built-in debugging circuit
5
;
2
indicates a central processing unit (CPU) of the microcomputer
1
;
3
indicates a bus interface;
4
indicates a memory; and
5
indicates a debugging circuit for debugging a program of the microcomputer
1
by inputting and outputting data via an external debugger and a trace bus. The debugging circuit
5
is provided with a DATA terminal for inputting and outputting multi-bit DATA to and from the external debugger, a CLK terminal for inputting and outputting a clock signal CLK, an OE terminal for inputting and outputting a control signal OE for controlling input and output of the DATA and the clock signal CLK, and a SYNC terminal for inputting and outputting a synchronization signal SYNC when the tracing is performed.
Numeral
6
indicates a register control circuit for receiving data from the DATA terminal when the external debugger outputs the data to the DATA terminal and for decoding the data;
7
indicates a download control circuit for receiving a program generated by a host computer via the external debugger and downloading the program to the memory
4
;
8
indicates a trace control circuit for notifying the external debugger of the operating status of the CPU
2
;
9
indicates a comparator for comparing an address at which the program is executed with preset data in order to recognize the operating condition of the CPU
2
; and
10
indicates a register circuit.
A description will now be given of the operation according to the related art.
The debugging circuit
5
built in the microcomputer
1
mainly provides the following functions.
Communication Between the External Debugger and the Debugging Circuit
5
When the external debugger outputs the data to the trace bus under the control of the host computer, the register control circuit
6
of the debugger circuit
5
receives the data via the DATA terminal for decoding so as to determine the destination of the data.
Depending on the result of determination, the register control circuit
6
outputs the data to the download control circuit
7
, the trace control circuit
8
, the comparator
9
or the register circuit
10
.
When the incoming data requests reading of data stored in the register circuit
10
, the register control circuit
6
reads the data stored in the register circuit
10
.
Downloading
When the external debugger outputs the program generated by the host computer to the trace bus under the control of the host computer, the download control circuit
7
of the debugger circuit
5
receives the program via the DATA terminal.
The download control circuit
7
downloads the program to the memory
4
by using the control bus, the address bus ADCPU, and the data bus DB.
Tracing
The trace control circuit
8
recognizes the operating condition of the CPU
2
by capturing signals on the control bus, the address bus ADCPU and the data bus DB, which connect the CPU
2
and the bus interface
3
, and outputs the operating condition of the CPU
2
to the external debugger via the DATA terminal and the trace bus.
Breaking
When the external debugger outputs the address at which the program is executed and the data to the comparator
9
under the control of the host computer, via the CLK terminal, the DATA terminal, the OE terminal and the SYNC terminal, the address and the data being specified by the host computer, the comparator
9
compares the status of the address bus ADCPU with the written address.
When they match, the comparator
9
executes an interrupt processing program downloaded to the memory
4
by outputting an interrupt request to the CPU
2
. For example, the comparator
9
enables the CPU
2
and the external debugger to transfer data via the register circuit
10
.
The following steps for program debugging are taken using the functions described above.
(1) The host computer generates a program.
(2) The program is downloaded to the memory
4
of the microcomputer
1
.
(3) The host computer requests execution of the program and keeps track of the operating conditions of the microcomputer
1
from a trace output from of the debugging circuit
5
.
(4) A break interrupt is generated at a program address specified by the host computer. In this interrupt process, the host computer communicates with the debugging circuit
5
via the external debugger so as to learn the status of the microcomputer
1
.
FIG. 8
shows the internal construction of the trace control circuit
8
of FIG.
7
. Referring to
FIG. 8
, numeral
11
indicates a branch event generation circuit for generating an event necessary for execution of a branch trace in accordance with a control signal output from the CPU
2
to the control bus to require execution of the branch instruction. Numeral
12
indicates a status generation circuit for generating status information ST indicating the branch trace;
13
indicates an AND circuit for ANDing a synchronization signal SYNC_CPU occurring during the execution and a basic clock P
1
of the CPU
2
, and for outputting. BRAS_CLK. Numeral
14
indicates a branching source address latch for latching a branching source address in synchronization with BRAS_CLK.
Numeral
15
indicates an AND circuit for ANDing an operand fetch signal OPR occurring during the execution and the basic clock P
1
of the CPU
2
, and for outputting BRAD_CLK;
16
indicates a branching destination address latch for latching, in synchronization with BRAD_CLK, a branching destination address output from the CPU
2
to the address bus ADCPU;
17
indicates a logic circuit for outputting a selector control signal SELL in synchronization with a falling edge of a branching destination signal RCLR occurring subsequent to the execution of the branch instruction; and
18
indicates an AND circuit for ANDing the selector control signal SELL and the basic clock P
1
of the CPU
2
, and for outputting a trace memory write signal TRW
1
.
Numeral
19
indicates a CPU access event generation circuit for gen

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