Method of fabricating nitride read only memory

Details Method of fabricating nitride read only memory Method of fabricating nitride read only memory

2002-08-19

2003-09-30

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S441000, C438S978000

Reexamination Certificate

active

06627500

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a memory, and more particularly, to a method of fabricating a nitride read only memory (NROM).
2. Description of the Related Art
Due to the data storage characteristics, the read only memory has been widely applied. The current read only memory includes the mask read only memory (mask ROM), the programmable read only memory (PROM), the erasable programmable read only memory (EPROM), the electrically erasable programmable read only memory (EEPROM), and the flash electrically erasable and programmable read only memory (flash EEPROM).
The erasable programmable read only memory has the programming function, erasable function and data retention after power source interrupt. To the equipment that requires the function of data retention and refresh such as the basic input output system (BIOS) in a personal computer and the electronic equipment, such memory has been commonly used. Especially, for the electrically erasable programmable read only memory that has the in-circuit electrical programming and electrical erase functions superior to the erasable programmable read only memory, it has becomes the orientation of future research and development.
A typical electrically erasable programmable read only memory uses doped polysilicon to fabricate a floating gate and a control gate. While programming, the electrons injected into the floating gate are evenly distributed in the polysilicon floating gate. Once defects exist in the tunneling oxide under the polysilicon floating gate, a leakage current is easily caused to affect the device reliability.
Currently, a nitride read only memory has been developed. The nitride read only memory has a trapping dielectric sandwiched structure on a substrate. The trapping dielectric sandwiched structure includes a structure of insulation layer-charge trap layer-insulation layer, for example, oxide-nitride-oxide (ONO). The charge trap layer has the function equivalent to the floating gate in the normal electrically erasable programmable read only memory. Yet, the control gate is still made of polysilicon. While programming the device by applying a voltage to the control gate and the floating gate, the electrons in the channel region close to the drain region are injected to the charge trap layer. Since silicon nitride has the characteristics of trapping electrons, the electrons injected into the charge trap layer are not uniformly distributed therein. Instead, the electrons injected to the charge trap layer are localized in an area with a Gaussian distribution. Therefore, the sensitivity towards the defects of the tunneling oxide layer is smaller, so that the leakage current is less possible to occur.
The conventional method of fabricating nitride read only memory is illustrated as
FIG. 1A
to FIG.
1
C. In
FIG. 1A
, a substrate
100
is provided. The substrate
100
is delivered to a furnace to form an oxide layer
102
. A charge trap layer
104
of which the material includes nitride, and an oxide layer
106
are formed on the oxide layer
102
by chemical vapor deposition. An oxide-nitride-oxide trapping dielectric sandwiched structure is thus formed on the substrate
100
.
In
FIG. 1B
, a patterned photoresist layer
108
is formed on the oxide layer
106
. An ion implantation step is performed on the substrate
100
. Using the photoresist layer
108
as a mask, an anisotropic etching step is performed to remove portions of the oxide layer
106
and the charge trap layer
104
to form an opening
110
.
In
FIG. 1C
, the substrate
100
is delivered in a furnace again. A thermal oxide layer
112
is formed in the opening
110
as an embedded drain region insulation layer. A polysilicon layer
114
is further formed as a control gate by chemical vapor deposition.
The above method for fabricating the nitride read only memory has the following drawbacks.
The opening formed by etching the oxide layer and the charge trap layer normally has a sidewall vertical to the substrate as shown in FIG.
1
B. In the subsequent processes for forming the embedded drain insulation and the control gate, the embedded drain insulation layer is likely to have an elliptic shape due to the bird's beak effect. Moreover, the charge trap layer and the oxide layer on the opening sidewalls are crowded and pushed up by the elliptic embedded drain insulation layer. As shown in
FIG. 1C
, a contact between the charge trap layer
104
and the polysilicon layer
114
is formed to cause the device defect.
Though the electrons are concentrated in a local area of the charge trap layer, a gradual diffusion is inevitable for a long operation period. Consequently, as the charge trap layer is in direct contact with the polysilicon layer, the electrons flow to the polysilicon layer to cause the data loss.
SUMMARY OF INVENTION
The invention provides a method of fabricating a nitride read only memory. A substrate is provided. A first insulation layer, a charge trap layer and a second insulation layer are formed as a dielectric trapping sandwiched structure on the substrate. A pattern transfer layer is formed on the second insulation layer. Using the pattern transfer layer as a mask, the substrate is implanted to form a source/drain region. The pattern transfer layer is further used as a mask to etch the second insulation layer and the charge trap layer to form an opening. The pattern transfer layer is removed first, and then a wet etching step is further performed to remove a part of the charge trap layer on the sidewalls of the opening. As a result, an opening with indented sidewalls is formed. An embedded thermal oxide layer is formed to fill the opening. The indented sidewalls are completely sealed by the thermal oxide layer, and the charge trap layer is sealed with the first and second insulation layers and the thermal oxide layer. A conductive layer is then formed over the substrate as a control gate of the device.
As mentioned above, after forming the opening by etching the second insulation layer and the charge trap layer, a wet etching process is further performed on the opening. A part of the charge trap layer exposed by the opening is removed to result in an opening with an indented sidewall. Therefore, in the subsequent process, the embedded drain insulation layer with an elliptic shape due to the bird's effect seals the opening sidewall completely, such that the charge trap layer is sealed with the first and second insulation layers, and the embedded drain insulation. There is thus no contact between the conductive layer and the charge trap layer to maintain the integral of the device.
Since the charge trap layer has no contact with the control gate, the electrons in the charge trap layer have no access to flow over the control gate. Therefore, the data loss is prevented, and the capability of data retention is reinforced.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 4407696 (1983-10-01), Han et al.
patent: 4708768 (1987-11-01), Enomoto et al.
patent: 5132241 (1992-07-01), Su
patent: 5236862 (1993-08-01), Pfiester et al.

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