Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-10-08
2003-08-12
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
06605521
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming an oxide film on a side wall of a gate structure, in particular, to a method for preventing abnormal oxidation of a side wall of a gate silicide layer in the post-etching oxidation treatment after forming a gate structure by an etching treatment.
In the field of semiconductor technology, a thinner and smaller element is being developed. For example, the latest DRAM cell has a gate insulating film of about 50 to 80 angstrom thickness and a metal silicide layer of about 500 to 1000 angstrom thickness. Furthermore, the width thereof is about 0.35 &mgr;m. The gate structure generally includes a thin SiO
2
gate insulating film (gate insulating film)
26
, N
+
silicon gate conductor layer (gate conductor layer)
28
, a tungsten silicide (WSi) layer (metal silicide layer)
30
, and a silicon nitride (SiN) cap layer (cap layer)
32
successively laminated on a silicon semiconductor substrate
12
as shown in FIG.
15
. The configuration including an N
+
silicon gate conductor layer
28
and a WSi layer
30
formed thereon is generally called a polycide (WSi/N
+
silicon) gate layer. Conventionally, in order to form the gate structure shown in
FIG. 15
, a thin SiO
2
film (insulating film)
14
is formed on a silicon semiconductor substrate by heat oxidation followed by an N
+
silicon conductor layer (conductor layer)
16
by the CVD method, a tungsten silicide (WSi) layer (metal silicide layer)
18
by the sputtering method, and a silicon nitride (SiN) layer (cap layer)
20
by the LPCVD (Low Pressure CVD) successively as shown in FIG.
16
. Furthermore, a photo resist is applied on the laminated material layers to form a photo resist film
22
as shown in FIG.
16
. Then by patterning the photo resist film, a resist pattern is formed as shown in FIG.
17
. By patterning the laminated material layers by the RIE (reactive ion etching), using the resist pattern as the mask, the gate structure shown in
FIG. 15
is formed. However, since the side wall of the N
+
silicon conductor layer and the WSi layer is exposed as well as the surface of the silicon semiconductor substrate is exposed by the etching treatment, the silicon substrate surface is contaminated due to the entrance of impurity into the silicon substrate surface or damaged due to the etching treatment. In order to realize a good gate structure, the damage needs to be eliminated. To this end, conventionally, the RTP (rapid thermal processing) is conducted in a substantially oxygen (O
2
) 100% atmosphere as the post-etching oxidation treatment performed after the above-mentioned etching treatment so as to oxidize the exposed side wall of the N
+
silicon conductor layer and the WSi layer, and the exposed surface of the silicon semiconductor substrate. That is, by the post-etching oxidation heat treatment on the exposed side wall of the N
+
silicon conductor layer and the WSi layer, and the exposed surface of the silicon semiconductor substrate, an oxide film
34
is formed as shown in FIG.
18
. By the post-etching oxidation heat treatment, the above-mentioned damage caused by the etching treatment at the time of forming the gate structure can be eliminated. At the same time, by the above-mentioned post-etching oxidation heat treatment, the electric field strength is weakened by the bird beak
36
generated at the lower part of the polysilicon layer rim portion as shown in
FIG. 18
as well as the capacitance among the gate drains is reduced to shorten the access time.
However, in the above-mentioned conventional post-etching oxidation heat treatment, it is liable to generate abnormal oxidation
38
. The abnormal oxidation can be easily generated particularly at the side wall oxidation of the WSi layer as shown in FIG.
18
. That is, by the heat treatment in the oxygen atmosphere, WSi is decomposed to WO
3
and SiO
2
. WO
3
is evaporated and the SiO
2
film is formed on the side wall of the WSi layer. At the time of the decomposition, Si is supplied from the N
+
silicon conductor layer to the WSi layer so as to contribute to the SiO
2
film formation. The heat treatment is conducted conventionally in the substantially oxygen 100% atmosphere, that is, in an atmosphere with a strong oxidizing property. However, if the heat treatment is conducted in the substantially oxygen 100% atmosphere, that is, in an atmosphere with a strong oxidizing property, the reaction proceeds rapidly so that the Si supply from the N
+
silicon conductor layer to the WSi layer becomes insufficient so that formation of a good SiO
2
layer is difficult. On the other hand, since a large amount of WO
3
is evaporated due to the rapid reaction, consequently the oxide film is made porous. It further accelerates the oxidation to result in the abnormal oxidation of the side wall of the WSi layer as shown in FIG.
18
. The abnormal oxidation caused by the mechanism involves a serious problem particularly in the latest memory cell with a thin gate structure because the abnormal oxidation is more liable in a thinner film thickness and a smaller volume.
FIG. 19
is a cross-sectional SEM profile showing the state after the post-etching oxidation treatment of the WSi layer/polysilicon gate structure formed in the conventional method, and
FIG. 20
is a perspective SEM profile thereof. The abnormal oxidation can be observed remarkably in
FIGS. 19 and 20
.
The above-mentioned problem of the abnormal oxidation on the side wall of the WSi layer (metal silicide layer) of the gate structure is more serious in, in particular, WSi layer with smaller size and thickness. Furthermore, with an oxide film bump formed due to the abnormal oxidation, which protrudes onto the side wall of the WSi layer, the contact resistance to the gate is increased and the controllability of the bit line contact is deteriorated.
BRIEF SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, an object of the present invention is to provide a method for preventing abnormal oxidation in the post-etching oxidation heat treatment for eliminating the damage caused on the exposed side wall of the gate conductor layer and the metal silicide layer, and the exposed surface of the silicon semiconductor substrate by the etching treatment conducted at the time of forming the gate structure of the semiconductor device, in particular, for preventing abnormal oxidation of the side wall of the metal silicide layer.
The present invention comprises two steps of rapid thermal processing (RTP) for the rapid thermal processing for the post-etching oxidation to be conducted after the etching treatment for eliminating the damage caused by the etching treatment conducted at the time of forming the gate structure of the semiconductor device. A first step of the RTP is a process of annealing for 120 seconds in an inert atmosphere of 700 to 1000° C., and a second step of the RTP is a process of annealing for 22 seconds in an oxygen atmosphere of 1000 to 1150° C. By the two step heat treatment, the damage caused in the gate structure and the semiconductor substrate at the time of the etching treatment can be eliminated. By the heat treatment in the inert atmosphere in first RTP process, a thin oxide film can be formed on the side wall of the metal silicide layer. Then by the heat treatment in an oxygen atmosphere of 1000 to 1150° C., the above-mentioned thin oxide film can be thickened to a sufficient film thickness. Since a thin but stable oxide film is already formed on the side wall of the metal silicide layer in the first RTP process at the time of conducting the second RTP process, the abnormal oxidation cannot be generated.
According to the invention, a method of forming an oxide film on a gate structure side wall, comprising the steps of successively forming an insulating film, a conductor layer, and a metal silicide layer on a semiconductor substrate, forming a gate structure including a gate insulating film, a gate conductor layer, and a gate silicide layer by etching t
Ajmera Atul C.
Balasubramanyam Karanam
Katata Tomio
Ko Shang-Bin
Banner & Witcoff , Ltd.
Blum David S
Jr. Carl Whitehead
Kabushiki Kaisha Toshiba
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