Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-03-28
2003-04-22
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189070, C365S185090
Reexamination Certificate
active
06552937
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to a method and apparatus for implementing memory repair using column segmentation.
II. Description of the Related Art
In order to ensure proper operation, semiconductor devices are typically tested before being packaged into a chip. A series of probes at a test station electrically contact pads on each die to access portions of the individual semiconductor devices on the die. For example, in a semiconductor memory device, the probes contact address pads and data input/output pads to access selected memory cells in the memory device. Typical dynamic random access memory (“DRAM”) devices include one or more arrays of memory cells arranged in columns and rows. Each array of memory cells includes rows (word lines) that select memory cells along a selected row, and columns (bit lines or pairs of lines) that select memory cells along a column to read data from, or write data to, the selected memory cells in an memory array.
During a pretest, predetermined data is typically written to selected column and row addresses that correspond to certain memory cells, and then the data is read from those memory cells to determine if the read data matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects and the semiconductor device fails the test.
Many semiconductor memory devices include redundant columns of memory cells that can be employed to compensate for certain columns containing defective cells. As a result, by enabling such redundant circuitry, a tested memory device need not be discarded even if it fails a particular pretest. Thus, if a memory cell in a column of the primary memory array is defective, then an entire column of redundant memory cells can be substituted for the column of memory cells containing the defective cell.
For memory devices employing redundant columns, column segmentation is often used. Column segmentation involves partitioning each column of the primary and redundant memory arrays. Therefore, if a portion of a primary column is found to be defective, only that portion of the primary column need be replaced and by only a portion of a redundant column. This preserves redundant column space, as only a limited number of redundant columns need to be fabricated on a memory device. Therefore, a memory device with more defective primary columns than redundant columns need not be scrapped as long as the defective segments of the primary columns can be substituted by an available segment of a redundant column.
Traditional column segmentation is set uniformly across all primary and redundant columns. Thus, traditionally column segmentation provides several segments, where all of the rows of each particular column segment are arranged adjacent to one another and remain fixed in that arrangement. The arrangement is common across all primary and redundant columns. With this traditional fixed segmentation scheme it is possible, depending on the location of defective cells, to have fewer available redundant segments for repair than primary segments which need repair. In this case, the memory device would be unrepairable because some defective segments of the primary array do not have a substitute redundant segment available for repair. A more flexible and efficient column segmentation arrangement would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus which provides more efficient and flexible column segmentation in a memory device utilizing redundant columns. The present invention provides for a programmable column segmentation arrangement in which the particular rows associated with a column segment can be changed permitting more flexibility in primary column repair.
Thus, after the primary columns have been analyzed for cell failures and after various column segmentation arrangements have been tested for optimum efficiency, a column segmentation arrangement can be selected to best suit the cell failures of the memory device.
REFERENCES:
patent: 5457655 (1995-10-01), Savignac et al.
patent: 5619460 (1997-04-01), Kirihata et al.
patent: 5822256 (1998-10-01), Bauer et al.
patent: 6373758 (2002-04-01), Hughes et al.
patent: 6418068 (2002-07-01), Raynham
Ladner Brian J.
Penney Daniel B.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Dinh Son T.
Nguyen Tuan T.
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