Method of making transistors with gate insulation layers of...

Details Method of making transistors with gate insulation layers of... Method of making transistors with gate insulation layers of...

2002-05-14

2003-04-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000

Reexamination Certificate

active

06541321

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of making transistors with gate insulation layers of differing thickness.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background,
FIG. 1
depicts an example of an illustrative transistor
10
fabricated on a wafer or substrate
11
. The transistor
10
is comprised of a gate insulation layer
14
, a gate electrode
16
, sidewall spacers
19
and source/drain regions
18
. The gate electrode
16
has a critical dimension (gate length)
16
A. Trench isolation regions
17
are also formed in the substrate
11
. Also depicted in
FIG. 1
are a plurality of conductive contacts
15
formed in a layer of insulating material
21
. The conductive contacts
15
provide electrical connection to the source/drain regions
18
. As constructed, the transistor
10
defines a channel region
12
in the substrate
11
beneath the gate insulation layer
14
. The substrate
11
is normally doped with an appropriate dopant material, e.g., a P-type dopant such as boron or boron difluoride for NMOS devices, or an N-type dopant such as arsenic or phosphorous for PMOS devices.
In an effort to increase the performance characteristics of modern integrated circuit devices, the gate insulation layer
14
, which is typically comprised of silicon dioxide, may be formed as thin as 2.0-2.5 nm (20-25 Å), and further reductions are planned in the future. The thin gate insulation layer
14
enables higher transistor drive currents and faster transistor switching speeds. However, reducing the thickness of the gate insulation layer
14
to the levels described above may also lead to other problems. For example, at the operating voltages of some modern integrated circuit devices, a gate current, i.e., a current between the substrate
11
and the gate electrode
16
, may be established. Such a gate current is due, in part, to the reduced thickness of the gate insulation layer
14
, which tends to limit its ability to perform its intended function of electrically isolating the gate electrode
16
. This gate current can be problematic in many respects in that it may increase power consumption and off-state leakage currents for the transistor
10
.
However, in many modern integrated circuit devices, e.g., microprocessors, application-specific integrated circuits (ASICs), etc., there may be situations where the formation of such a very thin gate insulation layer
14
is not required for all circuits in the integrated circuit product. For example, with respect to a microprocessor, there may be some circuits on the microprocessor that are not part of the “critical path” as it relates to establishing the switching speed of the completed device. In other cases, there may be some circuits on the microprocessor where it may be desirable to have an increased gate insulation thickness for other reasons. For example, for a variety of input/output circuits that interface with external devices, it may be desirable to have a thicker gate insulation layer
14
to ensure that the gate current does not get excessively high. As another example, there may be some circuits that occupy a great deal of plot space on the integrated circuit device but, nevertheless, are not part of the critical path as it relates to establishing the operating frequency of the integrated circuit device. For example, in the case of a microprocessor, there may be many decoupling capacitor circuits that, while they occupy a great deal of plot space on the integrated circuit device, they are not part of the critical path for the microprocessor in terms of performance. In such a situation, if the decoupling capacitors were made with a very thin gate insulation layer, then the decoupling capacitor circuits would unnecessarily increase the gate current for the overall device and lead to some of the disadvantages outlined above.
Thus, in some modern integrated circuit devices, manufacturers have begun forming transistors with different gate insulation thicknesses for various circuits within the integrated circuit device, i.e., so-called dual gate oxide circuits, triple gate oxide circuits. That is, for at least some circuits, the gate insulation layer
14
for certain transistors
10
is formed to a very thin thickness, whereas other transistors in less critical circuits of the integrated circuit device have a thicker gate insulation layer
14
. For example, with reference to
FIG. 2
, a first transistor
22
has a relatively thick gate insulation layer
22
A, whereas a second transistor
24
has a relatively thin gate insulation layer
24
A. The relative thicknesses of the gate insulation layers
22
A,
24
A depicted in
FIG. 2
are exaggerated for purposes of clarity and explanation. As described above, the transistor
24
may form part of a critical path of the integrated circuit device in terms of performance, whereas the transistor
22
may not be in such a critical path, or it may otherwise be important to provide a relatively thick gate insulation layer
22
A for the transistor
22
, i.e., it may be part of the input/output circuitry for the integrated circuit product.
One illustrative process flow for forming the transistors
22
,
24
depicted in
FIG. 2
is as follows. Initially, the trench isolation regions
17
are formed in the substrate
11
. Thereafter, a sacrificial oxide layer (not shown) may be deposited or thermally grown above the surface of the substrate
11
. Next, a patterned layer of photoresist (not shown) is formed above the substrate
11
. The patterned layer of photoresist is used to expose selected portions of the substrate
11
where it is desired to form transistors having an increased gate insulation thickness, such as the transistor
22
depicted in FIG.
2
. After the masking layer is formed, an ion implant process is performed to implant fluorine atoms through the sacrificial oxide layer into the portions of the substrate
11
exposed by the patterned masking layer. Thereafter, the patterned photoresist masking layer is removed. Then, a wet etching process, typically a wet etching process using HF acid, is used to remove the sacrificial oxide layer and to generally clean the substrate
11
prior to the formation of the gate insulation layers
22
A,
24
A for the transistor devices
22
,
24
. Then, a thermal oxidation process is performed to form the gate insulation layers
22
A,
24
A depicted in FIG.
2
. The gate insulation layers formed in areas where fluorine is implanted into the substrate
11
are thicker because the implanted fluorine atoms enhance the oxidation rate of the silicon substrate
11
. After the gate insulation layers
22
A,
24
A are formed, traditional processing operations may be continued to form the transistors
22
,
24
.
Unfortunately, the aforementioned process flow is not without problems. For example, during the etching process, i.e., the HF acid etching process mentioned above that is performed to remove the sacrificial oxide layer, the trench isolation regions
17
that were previously exposed to the fluori

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