Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-01-28
2003-12-02
Nguyen, Coung (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S382000, C257S296000
Reexamination Certificate
active
06656791
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit with a resistor and a method for fabricating thereof.
2. Description of the Related Art
A semiconductor integrated circuit includes a cell array region consisting of a plurality of unit cells and a peripheral circuit region which is located in the outside of the cell array region and consists of semiconductor circuits which control operations and input/output of the unit cell, for example a driver, a buffer or an amplifier. Each of the semiconductor circuits used in the two regions includes a transistor which is an active device and a resistance which is a passive device, basically. Consequently, a manufacturing process of a semiconductor integrated circuit accompanies processes of forming a plurality of transistors and resistors. In addition when a semiconductor device is formed in a cell array region, another semiconductor device of the same kind is also formed in a peripheral circuit region simultaneously.
In general, a gate poly resistance device using a dummy gate electrode structure which is formed in a peripheral circuit region and is made of the same material with another gate electrode structure formed in a cell array region, a self-alignment contact poly plug resistor using a self-alignment contact plug which is formed between the dummy gate electrode structures and is made of the same material with another self-alignment contact plug formed in the cell array region, or a plate electrode resistor which is made of the same material as another plate electrode formed in a cell array region, such as, a titanium nitride layer and polysilicon, has been used in conventional semiconductor integrated circuits. The gate electrode structure and the dummy gate electrode structure each includes a gate insulating layer, a gate electrode, a capping layer formed on the top surface of the gate electrode, and a pair of spacers formed at each side of the gate electrode.
The resistor used in a peripheral circuit region is required to exhibit a value of several k&OHgr; or hundreds of k&OHgr;. When the gate polyresistor having a polycide structure is used, its length must be increased, because the gate polyresistor exhibits a low face resistance. Accordingly, the size of a semiconductor integrated circuit must be increased.
The above self-alignment contact plug resistor is formed in a peripheral circuit region at which another self-alignment contact plug, that is, a bit line contact plug, is formed in a cell array region. Subsequently, a bit line is formed in the cell array region and the peripheral circuit region, and then an impurity ion such as N+ or P+ is inserted into the bit line. The specific resistance of a material forming the self-alignment contact plug can be varied by a heat treatment subsequent to a doping process or an impurity ion inserting process. In addition, the heights of the self-alignment contact plug resistor in the peripheral circuit region the self-alignment contact plug in a cell array region are also changed according to conditions of mechanical and chemical grinding processes for forming the self-alignment contact plug. Accordingly, a resistance value of the self-alignment contact plug resistor is also changed.
This variation in the resistance value of the self-alignment contact plug resistor causes a certain property of a semiconductor device provided with the resistor to be unstable.
On the other hand, the plate electrode resistor have a lower resistance value than polysilicon, and then the thickness of a titanium nitride layer which is used as a main passage of electrons varies according to a process condition. Consequently, the width of a plate electrode can also be varied according to conditions of a light exposure process and a developing process which are used in photolithography. In addition, the titanium nitride layer and the polysilicon layer are patterned on the entire surface of a cell array region. However, in a peripheral circuit region, only a certain area in which a resistor will be formed later, is patterned, thereby bring about a loading phenomenon. Consequently it is difficult to obtain a resistor of a desired size.
When metal which is one of conductive materials is used as a plate electrode, the length of a plate electrode resistor must be increased, because metal have a low face resistance.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a resistor which can prevent or reduce its value variations according to manufacturing processes of a semiconductor integrated circuit and a method for fabricating the same.
Accordingly, to achieve the above object of the invention, there is provided a resistor which is made of a conductive substance, for example, polysilicon and is formed on the top of a dummy gate electrode structure, or another resistor which is made of a conductive substance, for example, polysilicon and is formed between two neighboring dummy bit line structures which are formed on the top of the dummy gate electrode structure.
The dummy gate electrode structure includes a gate electrode which is made of a polysilicon layer and a metal silicide layer having a high melting point, and a dummy gate capping layer which is formed on the top surface of the gate electrode. The dummy bit line structure includes a dummy bit line and a dummy bit line capping layer formed on the top of the bit line. The dummy gate capping layer and the dummy bit line capping layer are formed of a substance having a high etching selection ratio with respect to each insulating layer covering the dummy gate electrode structure and the dummy bit line structure, thereby preventing the height of a resistor from varying according to a process condition or reducing the variation range of the height.
In addition, the dummy bit line structure further includes spacers which are formed at each side of the dummy bit line and the dummy bit line capping layer formed on the top of the dummy bit line. Each of the spacers are made of a substance having a high etching selection ratio with respect to the insulating layer covering the dummy bit line structure. Consequently, the width of the resistor may be prevented from varying according to a process condition.
After the dummy bit line structures are formed in the peripheral circuit area at which the bit line is formed in the cell array region, the resistor is formed between the dummy bit line structures. Consequently, the resistor can not be influenced by heat generated from an impurity ion doping process and a subsequent heat treatment process. Therefore, the variation range of the specific resistance of the resistor can be reduced considerably.
REFERENCES:
patent: 5066997 (1991-11-01), Sakuria et al.
patent: 5895947 (1999-04-01), Lee et al.
patent: 6150689 (2000-11-01), Narui et al.
Shin Soo-Ho
Yang Won-Suk
Marger & Johnson & McCollom, P.C.
Nguyen Coung
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