Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-08-09
2003-08-26
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S503000
Reexamination Certificate
active
06611922
ABSTRACT:
REFERENCE TO MICROFICHE APPENDIX
A microfiche appendix, Appendix A, is included of a computer program listing. The total number of microfiche is 6. The total number of frames is 186. A second microfiche appendix, Appendix B, is also included of schematic diagrams. The total number of microfiche is 1 and the total number of frames is 23.
COPYRIGHT NOTICE
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.
1. Field of the Invention
This present invention generally relates to power systems. More specifically, the present invention relates the time synchronization to a universal time of monitors on the power system.
2. Background of the Invention
In a typical electrical distribution system, an electrical supplier or utility company generates and distributes electrical energy to consumers via a power distribution network. The power distribution network is the network of electrical distribution wires which link the electrical supplier to its consumers. Typically, electricity from the utility is fed from a primary substation over a distribution cable to several local substations. At the local substations, the supply is transformed by distribution transformers from a relatively high voltage on the distributor cable to a lower voltage which is supplied to the end consumer. From the substations, the power is provided to users over a distributed power network that supplies power to various loads. Such loads may include, for example, various power machines used by the end consumer.
As such, each load and generator in the system is tied together directly through wiring, or indirectly through transformers. When there is a change in load, a change in generating capacity or a problem in the system, the effects propagate from the source of the event to other parts of the system. For instance, a fuse blowing in a motor load may cause a voltage surge in the system which causes other loads to draw excess current and blow fuses down the line. Likewise, a generator may fall off line causing a voltage sag which causes other equipment to malfunction.
Since the electrical power system is complex and effects can propagate through the system quickly, e.g., in fractions of a second, it is often difficult to determine which device is the source of a fault and which are the victims. A fault includes, for example, a short circuit, a sudden large increase in load, the sudden loss of generating capacity, and a lightning strike to a transmission line. Such faults are detected, for example with a waveform recorder, included as part of a power monitor or revenue meter with power monitoring capabilities. The waveform recorder plots a waveform which represents an amplitude of voltage and current versus time. When the fault occurs, it causes the waveform of the electrical signal to deviate from its normal near sine wave. In addition, the root mean square (rms) voltage and current of the waveform can change.
Since the waveform is plotted against time, many power monitors include an internal clock that can indicate when the fault occurred. Information of when the fault occurred is used to determine the source of the fault by identifying the power monitor that first recorded the fault. Since it takes time for the fault to propagate through the electrical distribution system, the source fault is located closest to the power monitor that first detected the fault. Thus, to determine the source of the fault, the consumer identifies which power monitor recorded the fault first.
A problem exists in that the internal clock time of each power monitor often varies among monitors. For example, known internal clocks utilize a 32.768 kHz watch crystal and a periodic interrupt timer (PIT) to determine time. The PIT increments, or decrements, depending on the application, a clock register which holds a value representing the time of the internal clock. Accuracy of this PIT is determined by the accuracy of the 32.768 kHz watch crystal. Due to the crystal's impurities, age and an operating temperature, the crystal's accuracy is typically 10-50 parts per million (ppm), which equals 26.8 seconds-2.2 minutes variance per month. Thus, the internal clock lacks the accuracy required to timestamp events such as faults that propagate through the power system in mere fractions of seconds.
One way to avoid the time variance between power monitors is for a master clock to broadcast a time synchronization message to each power monitor in the communications loop. Upon receipt of the time synchronization message, each power monitor then sets its internal clock to match that of the time broadcast message. Thus, the internal clocks can be synchronized each time the broadcast message is received. Problems occur in that the clock will be discontinuous at each second boundary since the PIT that is driving the internal clock is asynchronous to the master clock. Also, the internal clock drifts from the master clock until the next time broadcast is received.
Another way to avoid time variance between power monitors is to synchronize the power monitors to an inputted line frequency. According to Independent System Operator (ISO) specifications, internal clocks of the power monitors must adjust to synchronize with ISO Grid Operation line frequency. Many utilities are required to control the line frequency so that a number of line frequency cycles in a one week time period are within 0.02% of the exact number of cycles expected for that time period based on the specified line frequency. For example, when the integrated time error exceeds +/−2 seconds, a signal is sent to all utilities connected to Western Systems Coordinated Council (WSCC) and the utilities bias the automatic control systems to correct the error. Since the line frequency fluctuates and is unpredictable, a problem exists in that the total error of the internal clock becomes the error of the crystal plus the error of the line frequency when the line frequency is measured in terms of internal clock ticks.
Accordingly, there is a need for a time synchronization device and method which provides for an accurate sequence of fault recording. As such, there is a need for a device and method that periodically synchronizes internal clock times of monitors to a universal time or line frequency. In addition, there is a need to synchronize internal clock times without causing discontinuities and drift.
SUMMARY OF THE INVENTION
Such needs are met or exceeded by the present method and time synchronization device for synchronizing internal clock times to a universal time. Such synchronization, as performed by the present invention, provides for an accurate sequence of fault recording. The present device and method speeds up or slows down the rate at which the internal clock time proceeds to avoid discontinuities and drift associated with merely changing the internal time to equal the universal time.
More specifically, a preferred embodiment of the present invention receives a time synchronization message from an entity at a first free running counter count. The time synchronization message contains the universal time when the time synchronization message was sent. Thereafter, the time synchronization message is processed at a second free running counter count to determine the universal time. The time of the internal clock is compared to the universal time plus a processing time which is determined by the difference between the second free running counter count and the first free running counter count. Finally, the predetermined rate of advance of the internal clock is adjusted based on the difference between the internal time and the universal time plus the processing time to receive the message containing the universal time.
In another embodiment, the internal clock of the pow
Jonker Rene T.
Lightbody Simon H.
Ozcetin H. Kurtulus
Van Doorn Peter M.
Brinks Hofer Gilson & Lione
Butler Dennis M.
Power Measurement Ltd.
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