Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-06
2003-06-10
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S278000
Reexamination Certificate
active
06576518
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing a semiconductor device, and more particularly to a manufacturing technique of stabilizing an operation of writing information into each of elements which constitute a mask ROM (Read Only Memory).
In order to shorten the TAT (Turn Around Time) of a mask ROM, various techniques of ion-implanting for writing information (which is also referred to as “program write” or “ROM write”) after an Al wiring has been formed are known. Referring to
FIGS. 9A
to
9
D, an explanation will be given of a conventional manufacturing technique.
Step 1: As seen from
FIG. 9A
, using the technique of thermal oxidation or CVD, a pad oxide film
52
of a silicon oxide film having a thickness of
25
nm is formed on a P-type semiconductor substrate
51
. The pad oxide film
52
is formed to protect the surface of the semiconductor substrate
51
.
Next, a silicon nitride film
53
which is an oxidation-resistant film is formed on the entire surface. Thereafter, lengthy stripes of openings
53
a
for forming element isolation films
54
are formed in the silicon nitride film
53
in a direction perpendicular to a paper face of this drawing.
Step 2: As seen from
FIG. 9B
, using the technique of LOCOS with the silicon nitride film
53
as a mask, the semiconductor substrate
51
is oxidized to form element isolation films
54
. At this time, oxide regions invades between the semiconductor substrate
51
and silicon nitride film
53
so that bird's beaks
54
a
are formed. Next, the silicon nitride film
53
and pad oxide film
52
are removed, and using the technique of thermal oxidation, a gate insulated film
55
having a thickness of 14 nm to 17 nm is formed. Using the technique of CVD, a poly-Si film having a thickness of 350 nm is formed, and phosphorus is doped to form an N-type conductive film
56
.
Step 3: As seen from
FIG. 9C
, the conductive film
56
is etched in lengthy strips in a direction orthogonal to the element isolation films
54
(it should be noted that the etched region, which is in parallel to the paper face, is not illustrated) to form gate electrodes
56
a,
which serve as word lines. Using the gate electrodes
56
a
as a mask, P-type impurities such as boron are ion-implanted to form a source region and a drain region (which are not illustrated since they are formed below both ends of the gate electrode in a direction perpendicular to the paper face).
Through the process described above, memory cell transistors arranged in a matrix shape are formed. An interlayer insulating film
57
having a thickness of 500 nm of a silicon oxide film is formed on the entire surface. Al wirings
58
in lengthy strips, which serve as bit lines, are formed above the element isolation films
54
, respectively in a direction perpendicular to the paper face. Until this step, the manufacturing process can be carried out irrespectively of what program should be written in the memory cell transistors. For this reason, the wafers can be previously manufactured. In this case, a silicon oxide film
59
serving as a protection film is formed on the entire surface.
Step 4: At the time when a program to be written is determined on receipt of a request from a customer, as seen from
FIG. 9D
, a photoresist
60
having openings
60
a
for writing a program for a mask ROM is formed. P type impurities such as boron are ion-implanted in the semiconductor substrate
51
immediately beneath the gate electrodes
56
a
by using the photoresist
60
as a mask so that predetermined memory cell transistors are depleted. Thus, the threshold voltages of the memory cell transistors are lowered so that a ROM data is written.
However, generally, the processing accuracy of the photoresist is low, e.g. 0.5 &mgr;m. Therefore, the openings
60
a
formed in the photoresist
60
provide a variation of 0.5 &mgr;n. Further, as described above, the element isolation film
54
has the bird's beak and hence is thinned at its end. Therefore, where there is a variation in the openings
60
a,
as seen from
FIG. 10
, as the case may be, implanted impurity ions penetrate the bird's beak
54
a
to reach the semiconductor substrate
51
beneath the element isolation film
54
, surrounded by circle A. Where such elements are adjacent to each other, a leak current flowing below the element isolation film
54
a,
as indicated by arrow, occurs between the adjacent elements. This leads to poor element isolation. The improvement of the processing accuracy of the photoresist mask leads to a great increase in cost.
Further, in the semiconductor device incorporating various transistors having different withstand voltages, the thickness of the gate insulated film is set according to the various transistors. For example, where the gate insulated films having two kinds of film thicknesses are to be formed, a thick gate insulated film is once formed on the entire surface, and is etched at the area(s) where a thin gate insulated film is to be formed, and further the thin gate insulated film is formed again.
In this case, when the thick gate insulated film is etched away, the element isolation film will be shaved. During such a process, the thickness of the element isolation film at an ROM part gradually becomes thin.
In the process in which the ROM will be made later, ion-implantation for data write is executed to penetrate an interlayer insulating film, gate electrode and gate insulated film. Therefore, this must be carried out at high energy of 1 MeV to 3 MeV. The ion implantation at such high energy increases the lateral diffusion of implanted ions. This also leads to the poor element isolation as described.
Further, the apparatus for executing ion-implantation at such high energy is generally expensive, which results in an increase in cost.
For the reasons described above, in order to prevent the poor element isolation, the element isolation film must be set in a width larger than a processing limit so as to give sufficient allowance. In addition, it is difficult to thin the element isolation film, which hinders miniaturization. This is a first problem to be solved.
When the interlayer insulating film
57
is etched, the etching does not advance along the edge of the photoresist
60
, the sectional shape of the opening is tapered toward the bottom. The ion-implanting in this state leads to inconvenience of poor write due to an etching remainder. This is the second problem to be solved.
In order to solve this problem, where the interlayer insulating film is etched using the photoresist as a mask to form a ROM write region, taking the narrowing of the ion-implanted region due to the tapered portion into consideration, the photoresist is formed so that the diameter of the opening is larger than that of the ion-implanted region.
Thus, the poor ROM write due to the etching remainder of the interlayer insulating film could be avoided.
The above method was suitable for the write for an element at an individual position. However, where the write is done for the regions of adjacent elements, this method gave rise to the following problem.
Specifically, as seen from
FIGS. 11A and 11B
, in order to carry out the ROM write for the regions where the elements to be written are adjacent, when interlayer insulating films
63
,
62
,
61
and a part of the interlayer insulating film
57
are etched using as a mask photoresist
64
(which has an opening
64
a
having a diameter (X
2
) wider than that (X
1
) of the ion-implanted region), a thin photoresist remains above the metallic wiring
58
arranged on such a region. Where the interlayer insulating films are etched using the thin photoresist as a mask, as the case may be, the photoresist and interlayer insulating films fall down. This is a cause of a poor product. Incidentally,
FIG. 11A
is a sectional view taken in line A—A in
FIG. 11B
showing a semiconductor device in a multi-layer wiring structure.
SUMMARY OF THE INVENTION
In view of the first problem described above, in accordance with this invention, the method
Ariyoshi Junichi
Yamada Junji
Yamada Yutaka
Fish & Richardson PC
Sanyo Electric Co,. Ltd.
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