Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-05
2003-04-22
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S005000
Reexamination Certificate
active
06553562
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to photolithography, and in particular relates to the generation of mask layouts for use with dipole illumination techniques. In addition, the present invention relates to a device manufacturing method using a lithographic apparatus comprising a radiation system for providing a projection beam of radiation; a mask table for holding a mask, serving to pattern the projection beam; a substrate table for holding a substrate; and a projection system for projecting the patterned projection beam onto a target portion of the substrate.
BACKGROUND OF THE INVENTION
Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Furthermore, the constant improvements in microprocessor speed, memory packing density and low power consumption for micro-electronic components are directly related to the ability of lithography techniques to transfer and form patterns onto the various layers of a semiconductor device. The current state of the art requires patterning of CD's well below the available light source wavelengths. For instance the current production wavelength of 248 nm is being pushed towards patterning of CD's smaller than 100 nm. This industry trend will continue and possibly accelerate in the next 5-10 years, as described in the International Technology Roadmap for Semiconductors (ITRS 2000).
Lithographic methods aimed at improving resolution, while retaining acceptable process latitude and robustness are classified as Resolution Enhancement Techniques (RET's) and comprise a very wide range of applications. Examples include: light source modifications (e.g. Off-Axis Illumination), use of special masks, which exploit light interference phenomena (e.g. Attenuated Phase Shift Masks, Alternating Phase Shift Masks, Chromeless Masks, etc.), and mask layout modifications (e.g. Optical Proximity Corrections).
In an off-axis illumination regimen, as illustrated in
FIG. 1
, increased focus latitude and image contrast are achieved by capturing at least one of the first orders of the pattern spatial frequencies. As shown in
FIG. 1
, a typical off-axis illumination system includes in-part a light source
11
, a mask
12
, a lens
13
and the wafer
14
covered with photoresist. With dipole illumination, the light source is confined to two poles, in order to create the conditions for two-beam imaging with theoretical infinite contrast.
FIG. 2
illustrates the basic principles of dipole imaging. As shown, a dipole illumination system includes in-part a dipole aperture
16
(or other dipole generating means, such as a suitable diffractive optical element), a condenser lens
17
, a mask
18
, a projection lens
19
and the wafer
20
. The dipole apertures
16
can be of various shapes and orientations, e.g. horizontal, vertical or at any given angle. Exemplary dipole apertures
16
of various sizes and shapes are shown in FIGS.
3
(
a
)-
3
(
h
). A detailed description of the concepts of dipole illumination is set forth in U.S. patent application Ser. No. 09/671,802, filed Sep. 28, 2000, which is hereby incorporated by reference.
When dipole illumination is used, resolution is enhanced only for geometrical patterns with orientations perpendicular to the pole orientation axis. For example, a “horizontal” dipole allows the patterning of sub-resolution “vertica
Capodieci Luigi
Robles Juan Andres Torres
Van Os Lodewijk Hubertus
ASML Masktools B.V.
Dimyan Magid Y
McDermott & Will & Emery
Smith Matthew
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