Method for fabricating MOS field effect transistor

Details Method for fabricating MOS field effect transistor Method for fabricating MOS field effect transistor

1996-07-05

2003-04-01

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S307000, C438S527000

Reexamination Certificate

active

06541341

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method for fabricating a MOS field effect transistor (MOSFET) and, more particularly, to a method for fabricating a MOSFET with at least two dopants from Group V to reduce short channel effect.
BACKGROUND ART
In a conventional p-channel MOSFET, a substrate is ion implanted with arsenic (As) or phosphorus (P) dopants to prevent punch through effects. Alternatively, phosphorus P is halo-implanted into a substrate, as shown in
FIG. 1
, to form a halo structure around source and drain regions which reduces the short channel effect. This prevents the threshold voltage (vt) lowering phenomenon, for example, Vt roll-off phenomenon, caused by the reduction of the size of the semiconductor device into a-deep submicron. The halo structure also increases the current driving capability.
FIGS. 1A-1C
illustrate a method for fabricating a conventional p-channel MOSFET using a large angle tilt implanted punchthrough stopper (LATIPS) technology. An n+ LATIPS region
5
is easily formed by large-angle tilt (LAT) ion implantation without p+ ion implantation using a spacer, and the aforementioned LATIPS technology is the same as that for fabricating a conventional 0.5 &mgr;m CMOS having a 10 nm-thick gate oxide layer.
As shown in
FIG. 1A
, boron fluoride (BF
2
) at a dose and an energy level of 1.7×10
12
cm
−2
and 50 keV, respectively, is ion-implanted into an n-well
1
, resulting in a surface concentration of 1×10
16
cm
−1
, to form a counter-doped p-channel region
2
of 0.17 &mgr;m thickness. A gate oxide
3
is deposited on a p-channel region
2
, and then a gate pattern
4
with <100> orientation is formed on the gate oxide
3
.
As shown in
FIG. 1B
, phosphorus P (2×10
13
cm
−2
dose) is ion-implanted at a large angle tilt of 25° and at an energy level of 90 keV to form an n+ LATIPS region
5
in a predetermined portion of the n-well
1
and p-channel region
2
. The LAT ion implantation is repeated two to four times depending on the orientation of the gate pattern
4
.
As shown in
FIG. 1C
, boron fluoride BF
2
is ion-implanted at a dose of 3×10
15
cm
−2
and at an energy level of 40 keV, using the gate pattern
4
as a mask, resulting in a p+ source/drain region
6
having a junction depth of about 0.20 &mgr;m in a substrate portion on the right and left side of gate pattern
4
. A halo-structure n+ region
5
′ having a length of about 0.06 &mgr;m and an n-type peak concentration of about 1.5×10
17
cm
−3
is formed between the p-channel region
2
and the p+ source/drain region
6
, but closer to the p+ source/drain region
6
. Although the short channel effect is reduced, tilt E ion implantation is repeatedly performed based on orientation of the polysilicon gate, resulting in complex fabrication with increased cost.
Disclosure of the Invention
An advantage of the present invention is a simpler method of making a MOSFET with reduced short channel effect.
The above and other advantages of the invention are achieved, at least in part by a method of fabricating a field effect transistor comprising the steps of: a) doping an area of a substrate with at least two different dopants from Group V;. b) forming a gate on the area; and c) forming source and drain regions adjacent to the gate in the area.
Additional advantages , objects and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims


REFERENCES:
patent: 5081052 (1992-01-01), Kobayashi et al.
patent: 5185279 (1993-02-01), Ushiku
patent: 5413949 (1995-05-01), Hong
patent: 5464782 (1995-11-01), Koh
patent: 5548143 (1996-08-01), Lee
patent: 5605855 (1997-02-01), Chang
patent: 5614430 (1997-03-01), Liang et al.
“A New p-Channel MOSFET with Large-Tilt-Angle Implanted Punchthrough Stopper (LATIPS),” by Takashi Hori et al., IEEE Electron Device Letter, vol. 9, No. 12, Dec. 1988.

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