Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-29
2003-08-12
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S044000, C438S222000, C438S416000, C438S481000, C257S018000, C257S019000, C257S064000, C257S065000, C257S067000, C257S288000
Reexamination Certificate
active
06605498
ABSTRACT:
BACKGROUND OF THE INVENTION
1). Field of the Invention
This invention relates to the field of semiconductor manufacturing, and more specifically to a semiconductor transistor and its manufacture.
2). Discussion of Related Art
Integrated circuits are often manufactured in and on silicon and other semiconductor wafers. Such integrated circuits include literally millions of metal oxide semiconductor (MOS) field effect transistors, having gate lengths on the order of 0.05 microns. Such MOS transistors may include p-channel MOS (PMOS) transistors, and N-channel MOS (NMOS) transistors, depending on their dopant conductivity types.
Wafers are obtained by drawing an ingot of silicon out of a liquid silicon bath. The ingot is made of monocrystalline (single-crystal) silicon, and is subsequently sawed into individual wafers. A layer of silicon is then deposited over each wafer. Because the wafer is made of monocrystalline silicon, the deposition conditions can be controlled so that the layer of silicon deposits “epitaxially” on the monocrystalline silicon of the wafer. “Epitaxy” refers to the manner in which the silicon layer deposits on the wafer—the layer of silicon has a lattice which has a structure which follows a structure of a lattice of the monocrystalline silicon of the wafer. The layer of silicon is also substantially the same material as the monocrystalline silicon of the wafer, so that the lattice of the silicon layer also has substantially the same spacing as the spacing of the lattice of the monocrystalline silicon wafer.
A gate dielectric layer, a gate electrode, and spacers are subsequently formed on the layer of silicon. Ions are also implanted into the layer of silicon, to form source and drain regions on opposing sides of the gate electrode. A voltage can be applied over the source and drain regions. Current flows from the source region to the drain region through a channel below the gate dielectric layer when a voltage is applied to the gate electrode.
REFERENCES:
patent: 5908313 (1999-06-01), Chau et al.
Doyle Brian S.
Murthy Anand S.
Roberds Brian E.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Malsawma Lex H.
Smith Matthew
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