Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-02-06
2003-09-16
Le, Thong Quoc (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030, C365S225700
Reexamination Certificate
active
06621749
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Application No. 2001-7276, filed Feb. 14, 2001, the disclosure of which is hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit memory devices, and more particularly, to integrated circuit memory devices with redundant cells and methods of operation thereof.
Integrated circuit memory devices commonly include spare memory cells, i.e., redundant memory cells, which are used to replace primary (“normal”) memory cells that are defective. In some conventional memory devices, if at least one primary memory cell connected to a column select line CSL is defective, a column redundancy scheme is used, wherein the column select line CSL is replaced with a spare column select line SCSL. In other words, all memory cells connected to the column select line CSL are replaced with spare memory cells connected to the spare column select line SCSL, even if only one memory cell connected to the column select line is defective.
FIG. 1
shows a conventional one-to-one dedicated column redundancy scheme. Referring to
FIG. 1
, input/output blocks
11
and
13
each include a plurality of memory cells, column select lines CSL
11
, CSL
12
, CSL
21
, CSL
22
connected to the plurality of memory cells, and spare column select lines SCSL
11
, SCSL
12
, SCSL
21
, SCSL
22
. The column select lines CSL
11
, CSL
12
, CSL
21
, CSL
22
are connected to primary memory cells for normal operation of the primary memory cells. The spare column select lines SCSL
11
, SCSL
12
, SCSL
21
, SCSL
22
, which are connected to spare memory cells, i.e., redundant memory cells, are for used to replace defective memory cells.
The input/output block
11
includes one local input/output line LIO
1
and one global input/output line GIO
1
, and the input/output block
13
includes one local input/output line LIO
2
and one global input/output line GIO
2
. The local input/output line LIO
1
and the global input/output line GIO
1
input and output data into memory cells in the input/output block
11
, and the local input/output line LIO
2
and the global input/output line GIO
2
input and output data into memory cells in the input/output block
13
.
In the one-to-one redundancy scheme shown in
FIG. 1
, if a column select line CSL
11
in the input/output block
11
is defective, i.e., if at least one memory cell M
1
connected to the column select line CSL
11
is defective, the column select line CSL
11
is replaced with a spare column select line SCSL
11
. If a column select line CSL
21
in the input/output block
13
is defective, i.e., at least one memory cell connected to the column select line CSL
21
is defective, the column select line CSL
21
is replaced with a spare select line SCSL
21
. In other words, all memory cells connected to a defective column select line are replaced with spare memory cells connected to a spare column select line, even if only one memory cell connected to the column select line is defective.
In the one-to-one column redundancy scheme shown in
FIG. 1
, defective column select lines in a predetermined input/output block are replaced with only spare column select lines in the same input/output block. Because of this, the number of repairable column select lines in the input/output block depends on the number of spare column select lines available in the same input/output block.
FIG. 2
shows a conventional dataline column redundancy scheme. Referring to
FIG. 2
, in the dataline column redundancy scheme, input/output blocks
21
and
23
do not include spare column select lines. A redundant input/output block
25
includes spare column select lines.
The input/output block
21
includes one local input/output line LIO
1
, and the input/output block
23
includes one local input/output line LIO
2
. The redundant input/output block
25
also includes one local input/output line LIO
3
. The input/output blocks
21
and
23
and the redundant input/output block
25
share a global input/output line GIO.
Data is input into and output from memory cells in the input/output block
21
via the local input/output line LIO
1
and the shared input/output line GIO, and data is input into and output from memory cells in the input/output block
23
via the local input/output line LIO
2
and the shared input/output line GIO. Data is input into and output from memory cells in the redundant input/output block
25
via the local input/output line LIO
3
and the shared global input/output line GIO.
In the dataline column redundancy scheme shown in
FIG. 2
, if column select lines CSL
11
and CSL
12
in the input/output block
21
are defective, the column select lines CSL
11
and CSL
12
are replaced with spare column select lines SCSL
1
and SCSL
2
in the redundant input/output block
25
. If column select lines CSL
21
, CSL
22
, and CSL
23
in the input/output block
23
are defective, the column select lines CSL
21
, CSL
22
, CSL
23
are replaced with spare column select lines SCSL
3
, SCSL
4
, and SCSL
5
in the redundant input/output block
25
.
Accordingly, in the dataline column redundancy scheme shown in
FIG. 2
, defective column select lines in the input/output blocks are replaced with spare column select lines in the redundant input/output block. Therefore, repair efficiency and flexibility may be improved to some extent. However, like the column redundancy scheme shown in
FIG. 1
, all memory cells connected to a column select line are replaced with the spare memory cells connected to a spare column select line even if only one memory cell connected to the defective column select line is defective.
SUMMARY OF THE INVENTION
According to some embodiments of the present invention, an integrated circuit memory device includes a plurality of memory cells arranged as a plurality of blocks, each of the blocks including a plurality of primary memory cells that are coupled and decoupled to and from respective input/output lines responsive to a primary column select line and a plurality of redundant memory cells that are coupled and decoupled to and from respective ones of the input/output lines responsive to a redundant column select line. A column select circuit is coupled to the primary column select lines and to the redundant column select lines. The column select circuit drives a first primary column select line associated with a primary memory cell in a first block responsive to application of a first column address. The column select circuit simultaneously drives the first primary column select line and a first redundant column select line associated with a first redundant memory cell in a second block responsive to application of a second column address. The memory device further includes a plurality of sense amplifiers, and an input/output control circuit that is configurable to selectively connect the input/output lines to the sense amplifiers such that the first primary memory cell is coupled to a sense amplifier responsive to application of the first column address and such that the first redundant memory cell is coupled to the sense amplifier responsive to application of the second column address. The select circuit and the input/output control circuit may be operative to replace an individual primary memory cell with an individual redundant memory cell. In some embodiments, the input/output control circuit includes a plurality of switches operative to couple and decouple the input/output lines to and from the sense amplifiers. A switch control circuit controls the plurality of switches. The control circuit may be fuse-programmable.
Related operating methods are also described.
REFERENCES:
patent: 5455798 (1995-10-01), McClure
patent: 5761138 (1998-06-01), Lee et al.
patent: 6144593 (2000-11-01), Cowles et al.
patent: 6483773 (2002-11-01), Fister
patent: 11185493 (1999-07-01), None
patent: 1997-0029886 (1997-06-01), None
Notice to Submit Response, Korean Application No. 10-2001-0007277, Sep. 26, 2002.
Le Thong Quoc
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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