Method of fabricating a stack capacitor DRAM

Details Method of fabricating a stack capacitor DRAM Method of fabricating a stack capacitor DRAM

2001-06-18

2003-04-08

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S240000, C438S253000, C438S254000, C438S381000, C438S391000

Reexamination Certificate

active

06544832

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a structure and method for fabricating a stack capacitor DRAM, and more specifically, a stack capacitor DRAM having a capacitor over a bit-line and where the bit-line is formed using a damascene process.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memories (DRAMs) have memory cells that can only retain information on a temporary basis, even with power continuously applied. Accordingly, DRAM cells must be read and refreshed at periodic intervals in order to function as storage devices. Although DRAM cells typically take up less physical space than other types of memory storage devices such as Static Random Access Memories (SRAMs), it has been desirous to design and manufacturer ever smaller memory DRAM cells.
Like all random access memories, DRAMs are divided into separate storage cells of memory which are arranged in an array consisting of horizontal rows and vertical columns. Each cell shares electrical connections with all other cells in its row and column. Horizontal lines connected to all of the cells in the row are called word-lines. The vertical lines are called bit-lines. Each storage cell contains a capacitor and a transfer device. Data flows into and out of the cells along the bit-lines. The word-lines act as a switch and transfer data from the bit-line to the cell capacitor. Each memory cell therefore has a number of unique memory locations, or addresses, each of which can be addressed through the selection of the appropriate word-line and bit-line combination. In addition, there are also a number of support circuits at the periphery of the arrays of memory cells. Examples of typical support circuits include an address decoder, sense amplifier, and refresh circuitry.
In the ongoing drive to produce higher capacity DRAM storage devices, various capacitor structures have been developed to produce sufficient capacitances in a limited space. Each capacitor and transfer device which can be added to an array, effectively increases the memory capacity of the memory storage device. The capacitor can be located under the transfer device as a trench capacitor, or above the transfer device, as a stacked-capacitor. In both arrangements, one electrode of the capacitor is connected to the transfer device while the other electrode serves as a common plate joining all memory cells.
The stacked capacitor DRAM cell is itself one method of increasing memory capacity by shrinking the size of the memory cell without loss of storage capacity. In a stack capacitor DRAM cell, a capacitor structure is stacked on top of an access transistor formed on a semi-conductor substrate. The capacitor consists of a bottom electrode, a dielectric film, and an upper electrode. The bottom electrode is connected to the source region (diffused or ion implanted region) of the access transistor. This connection may be formed from a conducting material, such as polycrystalline silicon doped with an impurity, a metal, a conductive metal oxide, a conductive, a metal nitride, or some combination of the above. In a stack-capacitor DRAM, the bit-line can run either over the top electrode of the capacitor, or under the bottom electrode of the capacitor.
In a capacitor over bit-line configuration, a factor which affects the size of the DRAM cell is that the capacitor contact must be made in the space defined by the intersection of bit-lines and word-lines. Reducing the cell size effectively reduces the area for the capacitor contact, as the bit-lines and word-lines close in on this framed area. This reduced area for the capacitor contact reduces the tolerance of any mis-alignment of the capacitor contact to the bit-lines and word-lines during lithographic definition of the capacitor contact.
A damascene process is a process used in some aspects of semiconductor fabrication. It is a process of inlaying a metal into a predefined pattern, typically in a dielectric layer. It is typically performed by defining the desired pattern into a dielectric film; depositing metal over the entire surface by either physical vapor deposition, chemical vapor deposition, or evaporation; then polishing back the top surface in such a way that the top surface is planarized and the metal pattern is only located in the predefined regions of the dielectric layer. The damascene process has been used in manufacturing of metal wiring lines, including the bit-lines for a DRAM capacitor.
SUMMARY OF THE INVENTION
The present invention involves the fabrication of a capacitor contact for a stacked-capacitor DRAM cell with the capacitor over the bit-line, which is borderless to the word-line and either bordered or quasi-borderless to the bit-line, and in which the bit-line is formed by means of a damascene process.
The present invention involves a DRAM capacitor contact comprised of a silicon oxide layer with a trench having sidewalls and a form in the silicon oxide layer. A dielectric liner is coated on the sidewalls of the trench. A metal layer is then deposited between the sidewalls and polished to form a bit-line. one or more dielectric layers are deposited above the bit-lines and VIAs are formed in these layers. A sidewall is formed in the VIA above the bit-line and the VIAs are extended down to the silicon substrate and filled with a conductive material and planarized, forming the capacitor contact.


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