Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-30
2003-03-18
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S727000, C714S732000, C714S733000, C324S765010, C365S201000
Reexamination Certificate
active
06536007
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally concerns verification of logic in semiconductor devices, and, in particular, concerns automated techniques for isolation of logic faults.
2. Background Information
Fault isolation (FI) is essential in the production of modern integrated circuits. FI is used at different stages of the product cycle, including silicon debug, fabrication yield improvement and Low Yield Analysis, and customer returns. During the manufacturing process, there are many anomalies that can occur, resulting in logic faults known as open defects. Open defects cause interconnects between logic elements to be open or have high resistance, and occur due to manufacturing problems that cause missing conducting material or poorly formed vias and contacts, or due to reliability issues like thermal stress or electromigration. Open defects constitute a significant fraction of manufacturing defects. More importantly, open defects are hard to test and isolate, and have been the source of major yield issues (e.g., salicide cracking, missing vias, spongy vias and oval contacts) for semiconductor manufacturers. Thus efficient isolation or diagnosis of such defects plays a very important role in fabrication yield improvement and in identifying reliability issues during the qualification of products. The requirement for efficient diagnosis of open defects will become increasingly more critical with newer :,process technologies pushing the envelope on a number of metal layers.
Presently, the problem of diagnosing open defects is generally solved by two means. Conventional techniques that are currently deployed for random logic fault isolation include a combination of physical techniques (e.g., emission microscope and liquid crystal) and functional pattern analysis using a combination of RTL simulation, manual deductive reasoning and e-beam/laser voltage probing. This approach requires micro-architectural knowledge to analyze functional patterns and generally takes a long throughput (e.g., four or more weeks). Furthermore, success rates of physical techniques are reducing with increasing density, multiple metal layers and flip-chip packaging. In addition, alternative approaches that automatic the process of isolation using just the simple single stuck-at fault model has the disadvantage of low accuracy and imprecise isolation.
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