Semiconductor trench device with enhanced gate oxide...

Details Semiconductor trench device with enhanced gate oxide... Semiconductor trench device with enhanced gate oxide...

2001-11-20

2003-09-16

Le, Vu A. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S268000

Reexamination Certificate

active

06620691

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to MOSFET transistors and more generally to DMOS transistors having a trench structure.
BACKGROUND OF THE INVENTION
DMOS (Double diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) that use diffusion to form the transistor regions. DMOS transistors are typically employed as power transistors to provide high voltage circuits for power integrated circuit applications. DMOS transistors provide higher current per unit area when low forward voltage drops are required.
A typical discrete DMOS circuit includes two or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors it behaves as if it were a single large transistor. For a discrete DMOS circuit it is desirable to maximize the conductivity per unit area when the transistor matrix is turned on by the gate.
One particular type of DMOS transistor is a so-called trench DMOS transistor in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance. Examples of trench DMOS transistors are disclosed in U.S. Pat. Nos. 5,072,266 (Bulucea et al.), 5,541,425 (Nishihara), 5,430,324 (Bencuya), 5,639,676 (Hshieh et al.), 5,316,959 (Kwan et al.), 5,304,831 (Yilmaz et al.) and 5,866,931.
FIGS. 1A and 1B
depict one example of a conventional trench DMOS transistor
101
. The device is provided with a first trench
103
T
1
which is in the active region of the transistor and a second trench
105
T
2
which is in the termination region of the transistor.
Referring now to
FIG. 1B
, which is a cross-sectional view of the device of
FIG. 1A
taken along the line X-X′, the trenches reside in a substrate comprising an n+ doped layer
107
, an n doped epitaxial layer
109
, and a p type diffusion layer
111
of opposite conductivity. An n+ doped epitaxial layer
113
which overlies the p type diffusion layer serves as the source. The bottom of the trenches terminate in the n doped epitaxial layer. An insulating layer of silicon oxide
115
extends over the surface of both trenches. A source electrode
117
extends over the first trench, and a gate electrode
119
extends over the second trench. Both trenches are filled with polysilicon
121
and capped with BPSG
123
(boron phosphorosilicate glass).
In the device depicted in
FIG. 1B
, the average thickness t
ox1
of the silicon oxide layer overlying the first trench is equal to the average thickness t
ox2
of the silicon oxide layer overlying the second trench, that is, t
ox1
=t
ox2
. Devices of this type have at least one drawback that is an artifact of the methodology by which the device is manufactured. In particular, the device is typically subjected to at least two oxidation treatments during its manufacture, the first of which is employed for the removal of damages occurring at the time of silicon etching after formation of the trenches, and the second of which is used to form the silicon oxide layer. As shown in
FIG. 1C
, these oxidation steps produce a defect
125
in the form of a protrusion of the p type diffusion layer
111
into the silicon oxide layer
115
. This defect, often referred to as a “horn”, occurs in the upper end corner of the sidewall of the trench. The horn terminates in an acute angle. The thickness “t
h
” of the silicon oxide layer in the vicinity of the horn will be smaller than the average thickness t
ox2
of the silicon oxide layer positioned on the sidewall of the trench or on the surface of the p type diffusion layer.
During use, the n type polycrystalline silicon layer
121
that covers the horn and silicon oxide layer functions as a gate and is supplied with a predetermined potential. However, because of the shape of the horn, an electric field between the n type polycrystalline silicon layer and the substrate is concentrated in the vicinity of horn. Since the thickness of the silicon oxide layer in the vicinity of the horn is thin, the breakdown voltage of the silicon oxide layer is greatly reduced in this area.
Several approaches have been suggested in the art for dealing with this problem. One approach, which is disclosed in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-34, NO. 8, AUGUST, 1987, pp. 1681-P.1687, is directed toward the oxidation conditions of silicon. In this approach, oxidation is conducted at temperatures as high as 1100° C. According to the reference, a horn is not produced at these temperatures, and the upper end corner portion on the sidewall of the trench is rounded. Rounding the upper end corner portion on the sidewall of the trench relaxes the concentration of electric field at the portion, and the breakdown voltage of the silicon oxide layer positioned on the upper end corner portion of the sidewall of the trench is purportedly improved. However, this method is disadvantageous in that the use of such high temperatures in the oxidation steps can adversely affect on the structure of the impurity diffusion layers previously formed.
Another approach for avoiding the reduction in breakdown voltage of the silicon oxide layer at the upper corner portion of the sidewall of the trench is disclosed in laid open Japanese Patent Application Nos. 64-57623 and 63-166230. These references disclose a method of rounding the upper end corner portion on the sidewall of the trench by means of chemical dry etching. However, rounding the upper end corner portion on the sidewall trench in this manner is undesirable because, in order to relax the electric field intensity, the radius of curvature “r” of the corner portion must be increased. This in turn places a lower limit on the size of the device, which is a serious drawback in that it is desirable to minimize the size of the DMOS transistor.
U.S. Pat. No. 5,541,425 (Nishihara) discloses yet another approach which is intended to overcome the problems associated with segments of the gate oxide layer that have been thinned by two-dimensional oxidation. There, a method is disclosed whereby the top corner of the trench is rounded with an additional heavy arsenic implant through the use of an additional mask. However, the methodologies proposed therein are not suitable for a power MOSFET because the floating arsenic portion causes early avalanche breakdown. Moreover, the heavy doped arsenic portion induces silicon defects during subsequent oxidation processes such as sacrificial oxidation and gate oxidation.
U.S. Pat. No. 5,639,676 (Hshieh et al.) discloses a method for making a trenched DMOS transistor using seven masking steps. In accordance with the method, a masking step is used to produce an insulating oxide layer in the termination region which is thicker than the gate oxide layer in the active region of the transistor. However, as with the device depicted in
FIGS. 1A-C
, devices of this type are prone to reduction in breakdown voltage of the silicon oxide layer at the upper corner portion of the sidewall of the trench due to two-dimensional oxidation of the silicon oxide layer in this area.
There thus remains a need in the art for a trench DMOS device with improved gate oxide integrity and, in particular, a trench DMOS device having a gate oxide layer with improved breakdown voltage. There is also a need in the art for a method for making such a trench DMOS device, which method is applicable to power MOSFET devices. These and other needs are met by the present invention, as hereinafter disclosed.
SUMMARY OF THE INVENTION
The present invention relates to methods for creating trench DMOS devices with enhanced gate oxide integrity and, in particular, to

Affiliated with

Also associated with

Rating

Semiconductor trench device with enhanced gate oxide... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor trench device with enhanced gate oxide..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor trench device with enhanced gate oxide... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3076970