Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-07
2003-04-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S308000
Reexamination Certificate
active
06548350
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the field of integrated technology and relates, more specifically, to an integrated circuit configuration, that is to say a circuit configuration which is arranged in a substrate, with at least one capacitor.
An integrated circuit configuration of this type is described, for example, in European patent EP 0 415 530 B1 (see U.S. Pat. Nos. 5,126,810 and 5,196,365). The integrated circuit configuration is a memory cell arrangement wherein a memory cell comprises a transistor and a capacitor. The capacitor is embodied as a stacked capacitor and comprises a polysilicon structure with a plurality of polysilicon layers which are essentially arranged parallel one above the other and are connected to one another via at least one lateral support. The polysilicon structure is formed by the alternate deposition of polysilicon layers and SiO
2
layers, which can be etched selectively with respect thereto, on the surface of the substrate, patterning of the sidewall, production of layers coverings (spacers) made of polysilicon on at least one sidewall of the layer structure and selective etching-out of the SiO
2
layers. The polysilicon structure acts as a first capacitor electrode of the capacitor. The areas of the polysilicon structure are provided with a capacitor dielectric. Afterward, a second capacitor electrode of the capacitor is produced, which adjoins the capacitor dielectric. Despite the capacitor having a small space requirement, that is to say the capacitor having a small area when projected onto the substrate surface, the capacitor has a large capacitance since the surface area of the polysilicon structure is very large on account of the layers that are arranged one above the other.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating an integrated circuit configuration with at least one capacitor which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which, in comparison with the prior art, can have a smaller space requirement yet a high capacitance at the same time. With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing an integrated circuit configuration with at least one capacitor, which comprises:
providing a substrate having a surface defining a y-axis extending substantially perpendicular to the surface and defining a first height, a second height above the first height, and a third height between the first height and the second height;
producing a central part of a first capacitor electrode of the capacitor to extend from the first height to the second height, by forming a depression in an auxiliary layer applied on the substrate and filling the depression at least partly with conductive material;
after producing the central part, etching the auxiliary layer no deeper than to the third height;
producing a component of the integrated circuit configuration and connecting the component to the central part produced thereabove;
producing a spacer reaching at most to the second height, by depositing and etching back material as part of a spacing means, on uncovered parts of lateral areas of the central part;
growing conductive material, by selective epitaxy, on the central part but not on the spacing means;
depositing further conductive material substantially conformally;
etching back the conductive material to thereby produce from the conductive material
at least one side part of the first capacitor electrode beside the central part and spaced apart from the central part, such that the side part extends from the third height to the second height;
an upper part of the first capacitor electrode on the side part and the central part and connecting the side part and the central part to one another; and
to partly uncover a portion of the spacing means that projects laterally below the side part;
providing the first capacitor electrode with a capacitor dielectric; and
producing a second capacitor electrode adjoining the capacitor dielectric.
The resulting product is an integrated circuit configuration with at least one capacitor wherein the capacitor is arranged above a surface of a substrate. A y-axis runs perpendicularly to the surface of the substrate. A first capacitor electrode of the capacitor has a central part, which extends from a first height as far as a second height situated above the latter, with respect to the y-axis. The central part is connected to a component—arranged below it—of the integrated circuit configuration. The first capacitor electrode has at least one side part, which is arranged beside the central part and is spaced apart from the latter. The side part extends from a third height, which lies between the first height and the second height, as far as the second height. The first capacitor electrode has an upper part which is arranged on the side part and the central part and connects these to one another. The first capacitor electrode is provided with a capacitor dielectric. A second capacitor electrode adjoins the capacitor dielectric.
The method may also be summarized as follows: The capacitor is produced above a surface of a substrate. A central part of a first capacitor electrode of the capacitor is produced in such a way that it extends from a first height as far as a second height situated above the latter, with respect to the y-axis. A component of the integrated circuit configuration is produced and is connected to the central part produced above it. At least one side part of the first capacitor electrode is produced in such a way that it is arranged beside the central part and is spaced apart from the latter. The side part is produced in such a way that it extends from a third height which lies between the first height and the second height, as far as the second height. An upper part of the first capacitor electrode is produced in such a way that it is arranged on the side part and the central part and connects these to one another. The first capacitor electrode is provided with a capacitor dielectric. A second capacitor electrode is produced in such a way that it adjoins the capacitor dielectric.
Since the capacitor dielectric covers all the areas of the first capacitor electrode starting at least from the third height, and the second capacitor electrode covers the capacitor dielectric, a part of the second capacitor electrode is also arranged between the lateral part and the central part.
As a result of the cutout in the first capacitor electrode between the central part and the side part, the surface of the first capacitor electrode, which greatly influences the capacitance of the capacitor, is enlarged primarily by lateral areas of the side part and of the central part in comparison with a capacitor electrode without a cutout, without the space requirement of the capacitor being increased. The larger the distance between the third height and the first height, the larger the capacitance of the capacitor.
A particularly large capacitance of the capacitor is obtained if the third height is nearer to the first height than to the second height.
The first capacitor electrode can be produced for example with the aid of a spacing means. To that end, an auxiliary layer is produced above the substrate. The central part is produced by producing a depression in the auxiliary layer and filling it with conductive material. The spacing means is formed in such a way that it adjoins lateral areas of the central part and projects laterally away from the central part below the third height. The upper part and the side part are produced in such a way that they adjoin the spacing means. The upper part adjoins the spacing means from above, while the side part laterally adjoins the spacing means and also adjoins from above the part of the spacing means which projects laterally away from the central part below the third height. The part of the spacing means which adjoins the lateral areas of the central part is c
Schumann Dirk
Sell Bernhard
Willer Josef
Greenberg Laurence A.
Hoang Quoc
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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