Trench gate fermi-threshold field effect transistors

Details Trench gate fermi-threshold field effect transistors Trench gate fermi-threshold field effect transistors

2000-11-22

2003-04-29

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000, C257S336000

Reexamination Certificate

active

06555872

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to transistor devices and fabrication methods therefor, and more particularly to field effect transistors and fabrication methods therefor.
BACKGROUND OF THE INVENTION
Field effect transistors (FET) have become the dominant active device for very large scale integration (VLSI) and ultra large scale integration (ULSI) applications, such as logic devices, memory devices and microprocessors, because the integrated circuit FET is by nature a high impedance, high density, low power device. Much research and development activity has focused on improving the speed and integration density of FETs, and on lowering the power consumption thereof. FETs also are widely used as power devices, such as power amplifiers. Much research and development activity has focused on improving the speed and efficiency of FETs that are used as power devices, particularly at high frequencies, for wired and wireless applications.
A high speed, high performance field effect transistor is described in U.S. Pat. Nos. 4,984,043 and 4,990,974, both by Albert W. Vinal, both entitled Fermi Threshold Field Effect Transistor and both assigned to the assignee of the present invention. These patents describe a metal oxide semiconductor field effect transistor (MOSFET) which operates in the enhancement mode without requiring inversion, by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. As is well known to those having skill in the art, Fermi potential is defined as that potential for which an energy state in a semiconductor material has a probability of one-half of being occupied by an electron. As described in the above mentioned Vinal patents, when the threshold voltage is set to twice the Fermi potential, the dependence of the threshold voltage on oxide thickness, channel length, drain voltage and substrate doping is substantially eliminated. Moreover, when the threshold voltage is set to twice the Fermi potential, the vertical electric field at the substrate face between the oxide and channel is minimized, and is in fact substantially zero. Carrier mobility in the channel is thereby maximized, leading to a high speed device with greatly reduced hot electron effects.
Notwithstanding the vast improvement of the Fermi-threshold FET compared to known FET devices, there was a need to lower the capacitance of the Fermi-FET device. Accordingly, in U.S. Pat. Nos. 5,194,923 and 5,369,295, both by Albert W. Vinal, and both entitled Fermi Threshold Field Effect Transistor With Reduced Gate and Diffusion Capacitance, a Fermi-FET device is described which allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor in order to support carrier conduction. Accordingly, the average depth of the channel charge requires inclusion of the permittivity of the substrate as part of the gate capacitance. Gate capacitance is thereby substantially reduced.
As described in the aforesaid '295 and '923 patents, the low capacitance Fermi-FET is preferably implemented using a Fermi-tub region having a predetermined depth and a conductivity type opposite the substrate and the same conductivity type as the drain and source. The Fermi-tub extends downward from the substrate surface by a predetermined depth, and the drain and source diffusions are formed in the Fermi-tub within the tub boundaries. The Fermi-tub forms a unijunction transistor, in which the source, drain, channel and Fermi-tub are all doped the same conductivity type, but at different doping concentrations. A low capacitance Fermi-FET is thereby provided. The low capacitance Fermi-FET including the Fermi-tub will be referred to herein as a “low capacitance Fermi-FET” or a “Tub-FET”.
Notwithstanding the vast improvement of the Fermi-FET and the low capacitance Fermi-FET compared to known FET devices, there was a continuing need to increase the current per unit channel width which is produced by the Fermi-FET. As is well known to those skilled in the art, higher current Fermi-FET devices will allow greater integration density, and/or much higher speeds for logic devices, memory devices, microprocessors and other integrated circuit devices. Accordingly, U.S. Pat. No. 5,374,836 to Albert W. Vinal and the present inventor Michael W. Dennen entitled High Current Fermi-Threshold Field Effect Transistor, describes a Fermi-FET which includes an injector region of the same conductivity type as the Fermi-tub region and the source region, adjacent the source region and facing the drain region. The injector region is preferably doped at a doping level which is intermediate to the relatively low doping concentration of the Fermi-tub and the relatively high doping concentration of the source. The injector region controls the depth of the carriers injected into the channel and enhances injection of carriers in the channel, at a predetermined depth below the gate. Transistors according to U.S. Pat. No. 5,374,836 will be referred to herein as a “high current Fermi-FET”.
Preferably, the source injector region is a source injector tub region which surrounds the source region. A drain injector tub region may also be provided. A gate sidewall spacer which extends from adjacent the source injector region to adjacent the gate electrode of the Fermi-FET may also be provided in order to lower the pinch-off voltage and increase saturation current for the Fermi-FET. A bottom leakage control region of the same conductivity type as the substrate may also be provided.
Notwithstanding the vast improvement of the Fermi-FET, the low capacitance Fermi-FET and the high current Fermi-FET compared to known FET devices, there was a continuing need to improve operation of the Fermi-FET at low voltages. As is well known to those having skill in the art, there is currently much emphasis on low power portable and/or battery-powered devices which typically operate at power supply voltages of five volts, three volts, one volt or less.
For a given channel length, lowering of the operating voltage causes the lateral electric field to drop linearly. At very low operating voltages, the lateral electric field is so low that the carriers in the channel are prevented from reaching saturation velocity. This results in a precipitous drop in the available drain current. The drop in drain current effectively limits the decrease in operating voltage for obtaining usable circuit speeds for a given channel length.
In order to improve operation of the Tub-FET at low voltages, U.S. Pat. No. 5,543,654 to the present inventor Michael W. Dennen entitled Contoured-Tub Fermi-Threshold Field Effect Transistor and Method of Forming Same, describes a Fermi-FET which includes a contoured Fermi-tub region having nonuniform tub depth. In particular, the Fermi-tub is deeper under the source and/or drain regions than under the channel region. Thus, the tub-substrate junction is deeper under the source and/or drain regions than under the channel region. Diffusion capacitance is thereby reduced compared to a Fermi-tub having a uniform tub depth, so that high saturation current is produced at low voltages.
In particular, a contoured-tub Fermi-threshold field effect transistor according to the '654 patent includes a semiconductor substrate of first conductivity type and spaced-apart source and drain regions of second conductivity type in the semiconductor substrate at a face thereof. A channel region of the second conductivity type is also formed in the semiconductor substrate at the substrate face between the spaced-apart source and drain regions. A tub region of the second conductivity type is also included in the semiconductor substrate at the substrate face. The tub region extends a first predetermined depth from the substrate face to below at least one of the spaced-apart source and drain regions, and extends a second predetermined depth from the substrate face to below the channel region. The second pre

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