Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-18
2003-05-13
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S402000, C257S392000, C257S410000
Reexamination Certificate
active
06563182
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and especially to a technique for independently controlling the threshold voltages of a plurality of MIS (metal insulator semiconductor) field-effect transistors (hereinafter referred to as “MISFETs”) comprised in a semiconductor device.
2. Description of the Background Art
FIG. 9
illustrates a schematic cross-sectional view of a conventional semiconductor device
1
P. The semiconductor device
1
P is a basic CMOS (complementary MOS) device comprising both an n-channel MOS (metal oxide semiconductor) field-effect transistor (hereinafter referred to as an “nMOSFET”)
10
P and a p-channel MOSFET (hereinafter referred to as a “pMOSFET”)
30
P. Such a semiconductor device
1
P is disclosed for example in Japanese Patent Application Laid-open No. 6-61437 (1994), FIG.
6
.
As shown in
FIG. 9
, a semiconductor substrate
2
P is divided into active regions by an isolation oxide film
3
P. A p-well
11
P for the nMOSFET
10
P is formed in one of the active regions of the semiconductor substrate
2
P, whereas an n-well
31
P for the pMOSFET
30
P is formed in another active region adjacent to the above one.
In the surface of the p-well
11
P, a pair of n-type impurity layers
12
P and
13
P are formed with a channel region sandwiched in between. A gate insulating film
14
P composed of a silicon oxide film such as a thermal oxide film is formed on the channel region in the p-well
11
P and a gate electrode
15
P is formed on the gate insulating film
14
P.
Similarly, in the surface of the n-well
31
P, a pair of p-type impurity layers
32
P and
33
P are formed with a channel region sandwiched in between. A gate insulating film
34
P composed of a silicon oxide film such as a thermal oxide film is formed on the channel region in the n-well
31
P and a gate electrode
35
P is formed on the gate insulating film
34
P.
For low resistance, the gate electrodes
15
P and
35
P are doped with impurities such as phosphorus or boron by ion implantation or the like.
An interlayer insulation film
4
P is formed over the whole surface of the semiconductor substrate
2
P to cover the gate electrodes
15
P and
35
P. The interlayer insulation film
4
P has formed therein contact holes which connect the impurity layers
12
P,
13
P,
32
P, and
33
P to wires
17
P,
18
P,
37
P, and
38
P, respectively.
For example when the gate electrodes
15
P and
35
P are doped with phosphorus, due to (the presence or absence of) the work function difference between the gate electrodes
15
P,
35
P and their opposing channel regions, the following operating discrepancy arises between the nMOSFET
10
P and the pMOSFET
30
P.
In the nMOSFET
10
P, since the gate electrode
15
P is formed on the p-well
11
P, a positive work function difference &Dgr;&PHgr;ƒ with respect to the p-well
11
P (or the substrate
2
P) arises between the gate electrode
15
P and the p-well
11
P. Accordingly, the energy band in the vicinity of the channel bends downwardly when the potential of the gate electrode
15
P is equal to the substrate potential. From this, an inversion layer can be formed by slightly applying a positive potential to the gate electrode
15
P.
In the pMOSFET
30
P, on the other hand, since the gate electrode
35
P is formed on the n-well
31
P, no work function difference with respect to the substrate
2
P arises between the phosphorus-doped n-type gate electrode
35
P and the n-well
31
P. Thus, the energy band in the vicinity of the channel is almost flat when the potential of the gate electrode
35
P is equal to the substrate potential. From this, for formation of an inversion layer in the pMOSFET
30
P, the gate electrode
35
P must be set at a fairly high negative potential. That is, the threshold voltage (hereinafter also referred to as a “threshold value”) is increased.
When both the gate electrodes
15
P and
35
P are doped with the same type of impurity, the threshold voltages of the nMOSFET
10
P and the pMOSFET
30
P are determined by the work function differences between the gate electrodes
15
P,
35
P and their opposing channel regions. That is, the conventional semiconductor device
1
P has difficulty in controlling the threshold values of the nMOSFET
10
P and the p-MOSFET
30
P to the proper values.
As a measure to resolve such a problem, there is a method for independently controlling the threshold values of the MOSFETs
10
P and
30
P by doping the gate electrode
15
P of the nMOSFET
10
P with phosphorus and doping the gate electrode
35
P of the pMOSFET
30
P with boron.
The boron implanted in the gate electrode
35
P will, however, diffuse (penetrate) into the channel region in a subsequent thermal treatment process and therefore it may cause problems such as an unintentional threshold-voltage increase. In next-generation MOSFETs, since a thin silicon oxide film of about 2 nm or less is used for the gate insulating film
34
P, the above boron penetration is more likely to occur and thus changes in MOSFET characteristics are taken as an important issue.
Other examples of the methods for independently controlling the threshold values of the MOSFETs
10
P and
30
P include adjustment of the amount of dopant in the channel region and doping of the channel region with a counter impurity. However, such methods cause a considerable change in the impurity concentration of the channel region, resulting in characteristic deterioration such as an increase in channel leakage. Therefore, it is difficult to accomplish a dramatic threshold voltage shift, and the like.
In a system LSI, for specifications reasons, MOSFETs for logic circuit, MOSFETs for memory cell, and MOSFETs for I/O circuit often have different threshold voltages. In such a case, also, the aforementioned difficulty in controlling the threshold voltages becomes an issue.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate; a first MISFET including a first gate insulating film formed on the semiconductor substrate; and a second MISFET including a second gate insulating film formed on the semiconductor substrate, wherein the first gate insulating film includes, at least in part, a first dielectric film containing first metal ions and having a relative dielectric constant of 8 or more, the second gate insulating film includes, at least in part, a second dielectric film containing second metal ions and having a relative dielectric constant of 8 or more, first doping is performed on the first dielectric film using at least one kind of first impurity metal ions whose valence number differs by 1 from that of the first metal ions, and/or second doping is performed on the second dielectric film using at least one kind of second impurity metal ions whose valence number differs by 1 from that of the second metal ions, and wherein due to the first and/or second doping, at least one of the density and polarity of charged defects differs between the first dielectric film and the second dielectric film.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the first dielectric film and the second dielectric film are made of the same material.
According to a third aspect of the present invention, in the semiconductor device of the second aspect, the first MISFET includes an n-channel MISFET, the second MISFET includes a p-channel MISFET, the at least one kind of first impurity metal ions includes third metal ions having a valence number greater than the first metal ions, the at least one kind of second impurity metal ions includes fourth metal ions having a valence number greater than the second metal ions, and when the first doping and the second doping are both performed, a concentration of the third metal ions is set to be not less than that of the fourth metal ions.
According to a fourth aspect of the present invention, in the semiconductor device of either the second or the third aspect, the first MIS
Landau Matthew C.
Lee Eddie
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