System architecture of semiconductor manufacturing equipment

Details System architecture of semiconductor manufacturing equipment System architecture of semiconductor manufacturing equipment

2000-10-05

2003-07-29

Hassanzadeh, Parviz (Department: 1763)

Coating apparatus

Gas or vapor deposition

Multizone chamber

C118S724000, C156S345310, C156S345320

Reexamination Certificate

active

06599368

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of semiconductor manufacturing. More specifically, the present invention relates to system architecture of semiconductor manufacturing equipment for ultra high system throughput with reduced cost.
2. Description of the Related Art Semiconductor substrates (wafers) typically have many layers deposited thereon for device fabrication. Depositing many layers of various films is typically performed using deposition systems with multiple chambers designed for various processes. One of the most important performance indexes of the semiconductor manufacturing system is the system throughput, which is typically described as number of wafers per hour (wph). A single bottleneck point typically limits the system throughput, and this bottleneck can be a process chamber or a cluster robot (either a buffer robot or a transfer robot). If the chamber process times are short enough, the theoretical limit of maximum system throughput of such process sequencing is mainly by robot swap speed and the number of swaps each robot needs to complete full sequencing.
Conventionally, the system architectures for depositing Cu barrier and seed layers on semiconductor wafers have 3 or 4 wafers swaps for buffer robot and 3 swaps for transfer robot. For the configuration having 3 swaps each for buffer robot and transfer robot, the robot-limited system throughput is much higher than the one with 4 swaps for buffer robot. However, problems occur when maximum allowed chamber time become too short to complete the process required.
Therefore, the prior art is deficient in the lack of an effective system or means for depositing Cu barrier and seed layers on semiconductor wafers with ultra high system throughput while the chamber time is sufficient for performing the processes. The present invention fulfills this long-standing need and desire in the art.
SUMMARY OF THE INVENTION
In one aspect of the present invention, there is provided a system architecture of semiconductor manufacturing equipment, wherein degas chamber(s) are integrated to the conventional pass-through chamber location.
In another aspect of the present invention, there is provided a system for depositing Cu barrier and seed layers on a semiconductor wafer. This system comprises a front opening unified pod(s), a single wafer loadlock chamber(s), a degas chamber(s), a preclean chamber(s), a Ta or TaN process chamber(s), and a Cu process chamber(s). The degas chamber is integrated to a pass-through chamber location.
In still another aspect of the present invention, there is provided a method of depositing Cu barrier and seed layers on a semiconductor wafer using the above-described system. This method comprises the steps of (1) loading the wafer to the degas chamber from the front opening unified pod through the single wafer loadlock chamber; (2) performing degas processing on the wafer in the degas chamber; (3) removing native oxide from the wafer surface in the preclean chamber; (4) depositing Ta or TaN on the wafer in the Ta or TaN process chamber; (5) passing the processed wafer through the degas chamber; (6) depositing Cu seed layer on the wafer in the Cu process chamber; and (7) transferring the processed wafer from the Cu process chamber to the front opening unified pod through the single wafer loadlock chamber, thereby obtaining a wafer with Cu barrier and seed layer deposition.
Other and further aspects, features, and advantages of the present invention will be apparent from the following description of the embodiments of the invention given for the purpose of disclosure.


REFERENCES:
patent: 4581248 (1986-04-01), Roche
patent: 5240556 (1993-08-01), Ishikawa et al.
patent: 5371042 (1994-12-01), Ong
patent: 5474410 (1995-12-01), Ozawa et al.
patent: 5558717 (1996-09-01), Zhao et al.
patent: 5609689 (1997-03-01), Kato et al.
patent: 5683561 (1997-11-01), Hollars et al.
patent: 5766360 (1998-06-01), Sato et al.
patent: 5855681 (1999-01-01), Maydan et al.
patent: 5855687 (1999-01-01), DuBois et al.
patent: 5925227 (1999-07-01), Kobayashi et al.
patent: 6183564 (2001-02-01), Reynolds et al.
patent: 6201999 (2001-03-01), Jevtic
patent: 6251759 (2001-06-01), Guo et al.
patent: 0 537 364 (1993-04-01), None
patent: WO 00/21120 (2000-04-01), None
patent: WO 00/30155 (2000-05-01), None
PCT search report mailed Aug. 21, 2002 for application PCT/US 01/42365.

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