Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1999-05-24
2003-03-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S785000
Reexamination Certificate
active
06532566
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to use of error control techniques to detect and correct errors in a digital signal, and to efficient use of Reed-Solomon error detection and correction.
BACKGROUND OF THE INVENTION
Approaches for error control encoding for computer communications have been proposed and used for more than 40 years. Error control is of increasing concern as the speed of digital signal transmission increases by factors of ten each decade. Several error control schemes, such as those developed by Reed-Solomon (RS) and by Bose-Chaudhuri-Hocquenhem (BCH), allow correction of “burst” errors of several consecutive bytes and are of special interest in computer communications. These error control schemes are powerful and allow detection and correction of isolated bit errors and burst errors involving several consecutive erroneous bits or bytes. However, the encoding and decoding procedures are often long and complex, which limits digital signal throughput at the transmitting end and/or at the receiving end where these error control methods are used. A Reed-Solomon error control procedure typically requires matrix multiplication, or its equivalent, of large row and/or column matrices as part of the syndrome processing. These multiplications require a relatively large gate count in an HDL (hardware description language) formulation and add substantially to the time required for such processing.
What is needed is an approach that allows reduction of the gate count for pairwise multiplication in a Reed-Solomon error control procedure and decrease of the time required to form and to sum these pairwise products. Preferably, the system should work with any reasonable coding block dimensions and with any primitive polynomial used for Reed-Solomon encoding.
SUMMARY OF THE INVENTION
These needs are met by the invention, which provides a method for reducing the number of gates required and for decreasing the time required to form sums of products of pairs of elements, by using a parallel process to calculate the checkbyte(s) in an ECC processing phase for digital signals. The coefficients needed to form the sums of products are built into and provided within the syndrome generator and checkbyte generator modules so that these coefficients need not be computed each time.
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S.B. Wicker, Error Control Systems for Digital Commun. and Storage, Prentice Hall, Upper Saddle River, NJ, 1995, pp. 84-85.
De'cady Albert
Lamarre Guy
Oak Technology, Inc.
Schipper John F.
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