Single event upset tolerant microprocessor architecture

Details Single event upset tolerant microprocessor architecture Single event upset tolerant microprocessor architecture

1999-12-15

2003-05-27

Treat, William M. (Department: 2783)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S733000, C714S736000, C712S227000

Reexamination Certificate

active

06571363

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is fault tolerant computing and more particularly microprocessors or digital signal processors that enable single event upset fault tolerance.
BACKGROUND OF THE INVENTION
Digital signal processor designs have improved steadily over the years, such that, ever increasing compute power (complexity) and improved clock rate performance have become the confident expectations of the user. This impressive evolution of capability has been made possible through the constant improvements in the producing of high density silicon devices which have, in turn, been made possible because of steady reductions in feature size of CMOS devices.
Processes are in place which are capable of producing deep-sub-micron devices. Deep-sub-mircon devices have feature sizes of less than two tenths of a micron. Using such devices of such high complexity on a single chip has necessitated the use of lower voltage power supplies. This is required both to reduce device power and to allow the devices to operate within the lower voltage stress limits of the smaller device sizes.
Deep-sub-micron devices have very low voltage threshold (V
T
) as well. This characteristic has made designing with deep-sub-micron devices a formidable new challenge. Lower threshold voltage translates to lower noise-immunity. With an enormous number of devices switching (changing states) simultaneously, high levels of ground and power supply noise are generated. The use of dynamic logic to improve performance and circuit size and the need to make speed critical circuit components as small as possible brings new concerns for noise-immunity and vulnerability to logic-state faults. These faults must be dealt with in a sound manner if system reliability is to be achieved.
In addition, other well-known noise sources become more significant at the deep-sub-micron level. These noise sources include: higher levels of cross-talk between adjacent signal metallization; charges generated at dynamic nodes by Alpha particles; electromagnetic radiation from external sources; and substrate noise injection.
While many new circuit techniques have been brought to bear on the problem, the fact remains that dynamic logic using deep-sub-micron devices will simply be subject to growing reliability concerns. Thus there is a need in the art to address the aggravated noise problems associated with the use of low supply voltages and extremely small devices (sub-micron devices) and dynamic logic. Using these techniques result in devices of higher circuit impedances that are more easily perturbed, particularly in a dynamic logic environment, by power supply noise, by charges generated by Alpha particles, by electromagnetic radiation and by substrate noise, as noted above.
SUMMARY OF THE INVENTION
In the absence of creative new techniques, designers have frequently conceded the performance advantages of the smallest possible devices and have designed using larger device sizes to achieve the needed lower impedance and higher drive strength to make circuits more robust in these higher noise environments. This invention brings novel and unique techniques to bear on the problem. Chiefly these are hardware and software innovations which allow use of aggressive circuit design practices to reduce product cost, yet provide major new improvements in digital signal processor reliability through the use of fault tolerant architecture, and error detection and correction algorithms.
Dynamic faults have long been the concerns of computer designers. Many applications for computers require such high reliability that must be detected and corrected without any final errors resulting even for infrequent noise generated faults. These applications are chiefly the ones where human life or enormous financial investment must be protected. Fault-tolerant computers have emerged to serve such applications. Fault-tolerant design is receiving ever-increasing attention and concern.
Fault-tolerant systems often involve basic changes in the hardware design, and even more often, utilize software which directs the machine to do redundant as well as mainstream calculations. The results of the mainstream and the redundant calculations are compared to detect and correct errors by re-initiating the offending calculations. Fault-tolerant design typically involves generation of “signatures” or results, the processor state, and storing of “checkpoints”. These checkpoints are the state of the machine at which the signature in question was generated. Error-detection-and-correction (EDAC) generally follows. Fault-tolerant design approaches often involve hardware and software techniques. These hardware techniques often incorporate in extremely high-complexity devices to provide for effective testing using a minimized test vector set to screen the highest number of possible fault occurrences. This is called test-compaction.
This invention uses a unique digital signal processor architecture, and further combines hardware and software in two separate approaches. These are: a hardware intensive solution technique with moderate use of software; and a software assisted solution which uses additional algorithm power to simplify the required hardware.
It is the further object of this invention to bring to bear a unique new principle, that is, redundancy-in-time. This contrasts to the prior art redundancy-in-hardware or redundancy-in-software. The invention allows for free use of aggressive circuit design techniques, such as employing the smallest possible device sizes and dynamic logic, but provides protection from the single-event-upset faults which can occur in such low noise immunity circuits. In the absence of the fault-tolerant EDAC techniques described in this invention, the reduced drive capability and resulting low noise immunity of these circuit techniques would render their use impractical because of the variety of noise sources which could otherwise cause unrecoverable errors.


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