Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-11
2003-01-07
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S384000, C257S410000, C257S411000
Reexamination Certificate
active
06504214
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a semiconductor device having a dielectric made from high-K material and a method of formation having a low thermal budget.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. For example, certain materials selected to be used in a down-scaled device may react with other materials when a thermal budget for the materials is exceeded (for example, and depending on the material, when an anneal cycle approaches about 1000° C.).
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that optimize scale and performance. There also exists a need for corresponding fabrication techniques to make those semiconductor devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a MOSFET device. The MOSFET includes a layer of semiconductor material; a gate formed over the layer of semiconductor material, the gate including a gate electrode and a gate dielectric formed from a high-K material, the gate dielectric separating the gate electrode and the layer of semiconductor material; and a source and a drain each formed by selective in-situ doped epitaxy and located adjacent opposite sides of the gate so as to define a body region from the layer of semiconductor material between the source and the drain and under the gate.
According to another aspect of the invention, a method of fabricating a MOSFET device. The method including providing a layer of semiconductor material; forming a layer of high-K dielectric material over the layer of semiconductor material; forming a gate electrode over the layer of high-K dielectric material; removing a portion of the layer of high-K dielectric material extending laterally beyond the gate electrode to form a gate dielectric, the gate electrode and the gate dielectric forming a gate having laterally opposed sidewalls; removing a portion of the layer of semiconductor material extending laterally beyond each sidewall of the gate to form a source recess and a drain recess in the layer of semiconductor material; and forming a source in the source recess and a drain in the drain recess using selective in-situ doped epitaxy.
REFERENCES:
patent: 5798555 (1998-08-01), Mishra et al.
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6020024 (2000-02-01), Maiti et al.
patent: 6171910 (2001-01-01), Hobbs et al.
patent: 6210999 (2001-04-01), Gardner et al.
patent: 6232641 (2001-05-01), Miyano et al.
patent: 6261887 (2001-07-01), Rodder
patent: 6300202 (2001-10-01), Hobbs et al.
patent: 6346438 (2002-02-01), Yagishita et al.
patent: 6407435 (2002-06-01), Ma et al.
patent: 2002/0031909 (2002-03-01), Cabral et al.
Xiang Qi
Yu Bin
Advanced Micro Devices , Inc.
Jr. Carl Whitehead
Renner , Otto, Boisselle & Sklar, LLP
Smoot Stephen W.
LandOfFree
MOSFET device having high-K dielectric layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOSFET device having high-K dielectric layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOSFET device having high-K dielectric layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3065694