Sidewall protection in fabrication of integrated circuits

Details Sidewall protection in fabrication of integrated circuits Sidewall protection in fabrication of integrated circuits

2002-05-15

2003-05-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S954000

Reexamination Certificate

active

06566196

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to fabrication of integrated circuits.
U.S. Pat. No. 6,013,551 issued Jan. 11, 2000 to J. Chen et al. (that is incorporated by reference herein) discloses the following fabrication process for a stacked gate flash memory. Silicon dioxide layer (“tunnel oxide”) is grown on a semiconductor substrate. A polysilicon layer (floating gate polysilicon) is deposited on the tunnel oxide and patterned. A dielectric layer (ONO, i.e. silicon dioxide/silicon nitride/silicon dioxide) is formed on the floating gate polysilicon. Another polysilicon layer (control gate polysilicon) and tungsten silicide are formed on the ONO layer. Then the tungsten silicide, the control gate polysilicon, the ONO, and the floating gate polysilicon are etched to define the floating and control gates. See also U.S. Pat. No. 6,130,129 (that is also incorporated by reference herein as background).
The integrated circuit fabrication technology offers many etching techniques. The ONO etch should provide a desired selectivity to underlying materials.
SUMMARY
Certain embodiments of the invention are defined by the appended claims which are incorporated into this section by reference. The remainder of this section summarizes some features obtained in some embodiments.
Some embodiments of the present invention allow the etch selectivity requirements to be relaxed for the etch of the ONO (or some other dielectric) that separates the floating gates from the control gates. Before the ONO etch, the control gates have been patterned, and their sidewalls are exposed. Before the etch of at least the silicon nitride portion of the ONO layer, a protective layer, e.g. silicon dioxide is grown on the sidewalls of the control gates. Therefore, the etch of the silicon nitride portion of the ONO layer does not have to be selective to polysilicon (or other material of which the control gates are formed). The silicon nitride can be etched by an isotropic etch (e.g. using SF
6
) instead of an anisotropic etch which could remove excessive amounts of the field oxide.
The invention is not limited to the particular materials or etching techniques described above, or to stacked gate or flash memories.


REFERENCES:
patent: 6013551 (2000-01-01), Chen et al.
patent: 6084265 (2000-07-01), Wu
patent: 6130129 (2000-10-01), Chen
patent: 6171909 (2001-01-01), Ding et al.
patent: 6211016 (2001-04-01), Wu
patent: 6218309 (2001-04-01), Miller et al.
patent: 6355524 (2002-03-01), Tuan et al.

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