Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-10
2003-03-25
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06537907
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to define a metal interconnect structure.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices using sub-micron features, have resulted in increasing semiconductor device performance, as well as decreasing processing costs for a specific semiconductor chip. Specific semiconductor fabrication disciplines, such as photolithography, and dry etching, have allowed micro-miniaturization to be realized. The development of more sophisticated exposure cameras as well as the use of more sensitive photoresist materials, have allowed sub-micron features, as small as 0.25 um, to be routinely defined in photoresist layers. In addition the advent of advanced dry etching tools and processes have allowed the photoresist sub-micron features to be successfully transferred to underlying materials, such as metal layers, used for conductive features for advanced semiconductor devices. However when an aluminum based layer, overlying a barrier layer, such as titanium nitride, is to be patterned to create a narrow width, (0.25 um), metal interconnect structure for a semiconductor device, specific dry etching processes have to be used to avoid lateral etching, or undercutting of the aluminum based layer, during the definition of the underlying barrier layer.
This invention will describe a novel dry etching sequence in which the etch chemistry is changed, after definition of the narrow width, aluminum based interconnect structure, to allow the underlying barrier layer to be defined without attacking the already defined, overlying, narrow width aluminum based interconnect structure. This is accomplished by the addition of a fluorine containing component to the etch ambient, resulting in the formation of a sidewall layer on the exposed sides of the aluminum based interconnect structure, protecting the aluminum based structure from the etching sequence used to define the desired narrow width pattern in the underlying barrier layer. Subsequent removal of the photoresist pattern, also removes the protective sidewall layer. Prior art, such as Kadomura, in U.S. Pat. No. 5,217,570, describes a process sequence in which an aluminum layer, and an underlying barrier layer, are defined via dry etching procedures, however that prior art does not feature the unique in situ dry etching sequence, and details, supplied in the present invention.
SUMMARY OF THE INVENTION
It is an object of this invention to define a narrow width, metal interconnect structure, in a composite layer comprised of an overlying aluminum based layer, and an underlying barrier layer, via a two step, dry etching procedure.
It is another object of this invention to initially define the desired narrow width pattern in the aluminum based layer, using a chlorine based etchant, followed by the in situ addition of a fluorine based etchant, resulting in the formation of a self sidewall aluminum fluoride, (SSWAF), layer on the exposed sides of the defined aluminum based component, during the patterning of the underlying barrier layer.
It is still another object of this invention to remove the defining photoresist pattern after definition of the desired pattern in the aluminum based component, followed by definition of the underlying barrier layer, in the fluorine containing etchant, using the aluminum based structure as an etch mask, with the fluorine containing etchant allowing the formation of the protective SSWAF layer, on the sides, as well as on the top surface of the defined aluminum based structure, to be realized during the patterning of the underlying barrier layer.
In accordance with the present invention a method of defining an aluminum based interconnect structure, on an underlying barrier layer shape, featuring a first step used to define a pattern in the aluminum based layer, and featuring a second step, used to form a protective layer on the sides of the defined aluminum based component during the definition of the underlying barrier layer shape, is described. A first iteration of this invention features the use of a photoresist shape, used to define the desired narrow width pattern in an aluminum based layer, using a chlorine based etchant. With the photoresist shape in place, a fluorine based etchant is added to the chlorine based etchant, resulting in the formation of the SSWAF layer on the exposed sides of the defined aluminum based structure, during the patterning of the underlying barrier layer. Removal of the photoresist shape also results in removal of the SSWAF layer.
A second iteration of this invention features the use of a photoresist shape as an etch mask during the definition of the desired narrow width pattern in the aluminum based layer, via use of a chlorine based etchant. After removal of the photoresist shape a fluorine based etchant is added to the chlorine based etchant, allowing definition of the underlying barrier layer shape to be accomplished, during the simultaneous formation of the protective SSWAF layer, on all exposed regions of the aluminum based structure.
REFERENCES:
patent: 5066615 (1991-11-01), Brady et al.
patent: 5217570 (1993-06-01), Kadomura
patent: 5360510 (1994-11-01), Kadomura
patent: 5540812 (1996-07-01), Kadomura
patent: 5578163 (1996-11-01), Yachi
patent: 5976973 (1999-11-01), Ohira et al.
patent: 6017826 (2000-01-01), Zhou et al.
Stanley Wolf Silicon Processing for the VSLI ERA vol. 1 Lattice Press 1986 pp. 332 and 367.
Kuan Nien-Huai
Lo Chi-Hsin
Wei Horn-Jer
Ackerman Stephen B.
Blum David S
Jr. Carl Whitehead
Saile George O.
Taiwan Semiconductor Manufacturing Company
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