Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-16
2003-07-01
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S279000, C438S592000
Reexamination Certificate
active
06586305
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for producing an integrated semiconductor circuit.
During the production of integrated semiconductor circuits, transistors are formed on a semiconductor substrate. The normal transistors at the moment are generally metal oxide semiconductor field effect transistors (MOSFETs), whose center electrode, a gate electrode, is structured from a layer sequence of layers deposited on a substrate. Source and drain electrodes are then implanted into the substrate, on both sides of the gate electrode. The gate electrode essentially governs the switching response of the transistor. The desired switching response depends on the task associated with that transistor. In particular, the circumstance as to whether the transistor is a memory transistor for a memory cell or a logic transistor, which has to satisfy relatively stringent requirements for the transistor performance and in some circumstances also has to process analog signals, has major effects on the construction of the transistor, in particular on the composition of its gate layer stack.
Memory transistors that are produced using present-day technologies have, for example, a 60 to 80 nm thick lowermost gate layer on the gate oxide, which is covered by a nitride layer with a thickness, for example, of 200 nm.
Adjacent transistors on the substrate surface are generally disposed such that they are physically separated, and thus each has an individual source connection and a drain connection. In contrast, transistors for memory cells may be produced in pairs at a short distance from one another, with their adjacent gate layer stacks being separated only by a narrow area, which is used as a source contact or drain contact for both transistors at the same time. The electrode connection for connection of the common diffusion region is then introduced into the small space between the adjacent gate layer stacks. Since the gate oxide layer must be removed from the substrate surface between the gate layer stacks during this process, an etching process is carried out, in order to make it possible for the common electrode to make electrical contact between the adjacent gate layer stacks. The gate layer stack is itself attacked during the etching process, and this is undesirable. For this reason, the gate layer stack is protected by a thick nitride layer, which is deposited as the uppermost layer even before it is structured. During the subsequent etching process in order to make contact with the substrate implantations, the nitride layer protects the entire gate layer stack.
Transistors produced in this way may be disposed a short distance apart from one another in the areas of the substrate surface which are memory areas, and may be provided with a common source connection or drain connection. This construction in pairs is referred to as a borderless contact, and is used exclusively in the memory area, where the requirements for the switching response of the transistors are less stringent than in the logic area. Although the same transistors are produced in both areas, they are, however, produced a short distance apart from one another in pairs in the memory area, thus reducing the substrate surface area which is required for a memory cell. This allows particularly small memory cells to be produced.
In order to improve the switching response of a transistor, it is nowadays normal to dope the lowermost layers of a gate layer stack by ion implantation. Admittedly, in contrast to the situation with the source electrode and drain electrode, which are formed only by the introduction of implantations into the substrate, implantation of the gate electrode is not absolutely essential, since the gate electrode is used only to produce an electrical field through the gate oxide layer. However, the electrical potential of the channel area of the substrate located under the gate layer stack can be optimized by varying the electrical potential of the gate layer located above it. Such a potential shift is carried out, in a corresponding manner to the band scheme for electronic systems in solid bodies, by introducing dopings that cause an energy band shift in.the gate electrode. The band shift leads to a change in the ionization energy of the electrons in the lowermost gate layer at the boundary with the gate oxide located underneath it. The change in the ionization energy (work function) results in a change in the electrical potential of the channel area.
A band shift of a different magnitude is required depending on the type of transistor; in particular, it may be positive or negative.
N-channel transistors whose channel is formed by negative charge carriers are provided with n-doping for the gate electrode. In contrast, p-channel transistors are provided with p-doping. Different dopings for the n-channel transistors and p-channel transistors is optimum in cMOS circuits (complementary MOS).
Difficulties occur as soon as one integrated semiconductor circuit contains both memory transistors and logic transistors. Many modern integrated circuits, for example application specific integrated circuits (ASICs) contain memory areas that are referred to as embedded dynamic random access memories (embedded DRAMs) and are surrounded by logic areas. The two areas are produced by one and the same production process. In particular, the transistors for both areas are manufactured by one common process method.
In the memory area where the memory transistors are intended to be manufactured as far as possible using a borderless contact construction, that is to say in pairs with a common electrode between the gate layer stacks, the gate layer must be protected against contact etching by a thick nitride layer, typically with a thickness of 200 nm. In order to limit the depth of the contact to be filled in between the closely adjacent gate layer stacks, the lowermost gate layer, generally polysilicon, is deposited with a small layer thickness of only 60 to 80 nm. The small thickness results in that implantations cannot be introduced into the gate layer subsequently for an additional covering layer, without precluding doping of the channel area in the substrate. The doping must therefore be introduced into the gate at the same time that the layer is deposited. The polysilicon is thus deposited at the same time as the gate doping as the lowermost gate layer. In this method, the transistors that are to be manufactured in the memory area can be manufactured in pairs with a borderless contact.
In the logic area, whose transistors are manufactured at the same time as the transistors for the memory area, the construction of integrated circuits has the disadvantage that the same gate implantation is introduced in all the logic transistors, both in the n-channel transistors and in the p-channel transistors, and the gate implantation is matched to the memory transistors—generally exclusively n-channel transistors—which are disposed in the memory area. The p-channel transistors that are likewise disposed in the logic area thus receive negative doping in their gate electrodes, which results in a non-optimum ionization energy (work function) for the electrons in their gate layer.
This construction of an integrated semiconductor circuit with gate layer stacks which are optimized for transistors that are densely packed in pairs (borderless contact) in the memory area, both in the memory area and in the logic area, is referred to as a single work function structure, since the same value is set for the ionization energy in the lower gate layer and in the gate oxide in all the transistors in the integrated semiconductor circuit.
However, this structure is disadvantageous in the logic area.
In particular as transistors become increasingly physically smaller, with a lower operating voltage, the respectively optimum matching of the ionization energy, and hence the dual work function structure, become ever more important.
If, on the other hand, the transistors in the integrated semiconductor circuit are intended to
Fourson George
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Pham Thanh V
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