Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-23
2003-01-28
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000
Reexamination Certificate
active
06511882
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming an embedded non-volatile memory, and more particularly to a method for forming a plurality of separated spacer width in an embedded non-volatile memory to prevent leakage current.
2. Description of the Prior Art
Typical semiconductor memory utilized during microprocessor operation is volatile. That is in the case of power interruption, the data stored in the semiconductor memory is typically completely lost. One way to circumvent this problem is to provide separate backup of the memory, such as battery power or capacitor storage. An alternate technique is to make the memory fundamentally non-volatile. This option is highly desirable because non-volatile semiconductor memories would not only withstand, power interruption, but also would be stored or shipped without being energized.
Non-volatile memory devices are important for providing an advantage that random access memory (RAM), both dynamic and static, can't be provided. That is, non-volatile memory devices do not lose their memory even the power is turned off. RAM enables information to be both stored and read to a memory cell as dictated by a microprocessor. Read-only memory (ROM) is the most popular variety of non-volatile memory devices.
However, the flash memory is electrically re-programmable for a limited number of times. This makes it ideal for those applications where only a few changes in the programming of the system is for either the entire memory array or for blocks of it.
Besides, memory storage exists not only as stand-alone memory device, but also embedded in processor chips. The performance of an embedded flash can be better than other flash since bandwidth problems are reduced and interface circuit and package leads are eliminated. It can also have characteristic tailored to the specific application rather than being a standardized comprises between many factors such as high operating speed.
Referring to
FIG. 1A
, the substrate
100
is divided into at least two a memory array
100
a
and a logic device area
100
b
. The conventional method for forming the first dielectric layer (tunneling oxide layer)
102
a
on the substrate
100
by thermal oxidation. However, the dielectric constant value of first
102
a
and second dielectric layer
102
c
is about 3.8 to 3.9 and thermal oxidation is a high temperature process. Then, a charge storage layer
102
b
such as silicon nitride (SiN) formed on the first dielectric layer
102
a
by conventional CVD method (chemical vapor deposition method). Next, a second dielectric layer
102
c
formed on the charge storage layer
102
b
by conventional CVD method. The material of first
102
a
and second dielectric layer
120
c
is silicon oxide. According to the hot electron injection phenomenon (HEI), some hot electrons penetrate through the bottom first dielectric layer
102
a
, especially when first dielectric layer
102
a
is thin enough, and electrons are therefore collected in charge storage layer
102
b.
Referring to FIG.
1
B and
FIG. 1C
, a photoresist layer is formed on the second dielectric layer
102
c
. Then, an etching process is to remove the second dielectric layer
102
c
, charge storage layer
102
b
, and first dielectric layer
102
a
on logic device area
100
b
. Then, a gate oxide layer
104
is formed on the logic device area
100
b
, after the photoresist layer is removed, and a polysilicon layer
106
is deposited on the memory array
100
a
and logic device area
100
b
. Next, a word line is defined on memory array
100
a
and another photoresist layer is formed on the polysilicon layer
106
. Then, an etching process is performed on polysilicon layer
106
to form poly gate electrodes
106
on the memory array
100
a
and logic device area
100
b
simultaneously.
Referring to
FIG. 1D
, a silicon oxide is deposited to fill the pitch between the poly gate electrodes
106
. Then, an etching back process is performed on the silicon oxide to form spacers
110
on sidewall of the poly gate electrodes
106
. Then, a self-aligned silicide process is formed over the poly gate electrode
106
.
Referring to
FIG. 1E
is a vertical view of the memory device. The horizontal lines connected to all the cells in the row are called word lines
112
a
,
112
b
,
112
c
, and
112
d
, and the vertical lines (along which data flows into and out of the cells are called bit lines
114
a
,
114
b
,
114
c
, and
114
d
. The dotted line
116
is crosscut the word line
112
a
,
112
b
,
112
c
, and
112
d
. Due to the thickness of oxide
itride/oxide layer
102
is thinned; the salicide will pass through the oxide
itride/oxide layer
102
to the substrate
100
in self-aligned salicide process such that the semiconductor device will not be operated.
The most obvious limiting factor for an embedded flash memory is the relevant fabrication. In conventional fabrication, the transistors of memory array and logic device area are formed simultaneously; therefore, the quality of transistors of both memory array and logic device area can't be optimized at the same time. In other words, either performance of any transistors of logic device area is degraded or reliability of any memory array is degraded.
SUMMARY OF THE INVENTION
It is an object of this invention to provide separated spacer width to create an effective oxide thickness that can avoid a conduction film formed from self-aligned silicide process between bit line to bit line.
It is another object of this invention to prevent the leakage path is between bit line to bit line in self-aligned silicide process.
It is still another object of this invention to provide a separated adjust photo condition of memory array and logic device area to get optimum process windows.
It is still another object of this invention to improve the photo condition process windows of the word line and complementary metal-oxide semiconductor (CMOS) poly gate electrode to prevent the leakage between the bit line to bit line.
In one embodiment, a substrate has a bit line structure and a plurality of isolation devices. The substrate is divided at least a memory array and a logic device area. The transistors of memory array are formed firstly and the pitch width between poly gate electrodes is equivalent in memory array. And then, the transistors of logic device area are formed and the pitch width between the poly gate electrodes is not equivalent in logic device area. By using separated adjust photo condition of memory array and logic device area to get optimum process window and using separated spacer width in memory array and logic device area to avoid the leakage path in self-aligned salicide process.
REFERENCES:
patent: 5346842 (1994-09-01), Bergemont
patent: 5935875 (1999-08-01), Lee
patent: 6127224 (2000-10-01), Pio
patent: 6162675 (2000-12-01), Hwang et al.
patent: 6194267 (2001-02-01), Kaya
patent: 6261898 (2001-07-01), Wu
patent: 6297084 (2001-10-01), Joung et al.
patent: 6326669 (2001-12-01), Hwang et al.
Hwang Shou-Wei
Kuo Tung-Cheng
Liu Chien-Hung
Pan Shyi-Shuh
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