Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-04-25
2003-09-30
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S620000, C257S665000, C257S688000
Reexamination Certificate
active
06627917
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor fabrication. More particularly, the present invention pertains to apparatus and methods for burn-in of individual dies at the wafer level.
BACKGROUND
In conventional integrated circuit (IC) fabrication, an array of discrete ICs are formed as dies on the surface of a semiconductor wafer. Depending on the size of the die and the size of the wafer, hundreds of dies may be formed on a single wafer.
Before the dies are separated or “singulated” from the wafer, they typically undergo a testing procedure known as a wafer probe. A wafer probe tests for unwanted electrically open or shorted circuits by placing test probes across various conductive pads formed on the face of each die. Those dies that fail wafer probe are so indicated and excluded from further processing (e.g., packaging).
After such a wafer probe, the dies are singulated from the wafer, e.g., by sawing along scribe lines formed between the individual dies. The separated dies are then typically packaged to provide protection for the fragile circuits of the die as well as to provide a more convenient external lead system for electrical connection.
In its packaged form, each die undergoes more extensive functional testing to further screen out defective or sub-standard dies. In some instances, the die also undergoes reliability or “burn-in” testing. Static burn-in involves powering up the die for an extended period of time while dynamic burn-in additionally includes exercising some or all of the circuitry on the die. To accelerate the burn-in process, it may be conducted at elevated temperature. Burn-in is beneficial in applications where tolerance to chip failure is very low, e.g., medical devices, multi-chip modules, and the like.
While the burn-in methods described above satisfactorily produce packaged known good die, such post-singulation burn-in is inefficient for various reasons. For instance, time and expense are significant as post-singulation burn-in occurs on an individual or die-by-die basis. Further, because packaging constitutes a substantial portion of IC cost, detecting bum-in failures after packaging is not cost-effective. For these and other reasons, it is generally advantageous to burn-in dies and detect die failures prior to packaging or, where unpackaged, prior to incorporation into other modules.
One method for pre-packaged burn-in is disclosed in U.S. Pat. No. 5,489,538 to Rostoker, et al. The '538 patent describes a wafer level burn-in test where a series of dies are connected to an external current or signal source. The dies are then powered.
Another method for burning in dies at wafer level is disclosed in U.S. Pat. No. 5,600,257 to Leas et al. The '257 patent provides a test arrangement for simultaneously testing and burning-in a plurality of dies on an IC wafer.
Still other methods for powering one or more dies on a wafer prior to singulation are disclosed in U.S. Pat. No. 5,389,556 to Rostoker, et al. and U.S. Pat. No. 5,532,174 to Corrigan.
While these references describe the determination of potential die defects prior to packaging, problems remain. In particular, some of the methods provide only for serial testing of each die. This is time consuming given the number of dies on each wafer. Other methods and devices do not readily and easily identify whether a particular die was functional during the entire burn-in cycle. Thus, dies that may have had intermittent shorts or opens during burn-in may go undetected.
SUMMARY
Apparatus and methods for burn-in of dies according to the present invention avoids the above-mentioned problems. In one embodiment, a semiconductor wafer is provided. The wafer includes one or more conductive pads located in an inactive region of the wafer. The conductive pads are adapted to electrically couple to an external power supply. Also included is a plurality of dies in an active region of the wafer wherein each die includes a burn-in indicating apparatus. The burn-in indicating apparatus is adapted to indicate a burn-in parameter.
In one embodiment, the burn-in parameter is a period of time for which power is provided to the die by the external power supply. In another embodiment, the burn-in parameter is a period of time for which one or more circuits on the die is operating. The burn-in indicating apparatus, in one configuration, includes a one-bit counter adapted to switch when a pre-determined period of burn-in time has elapsed. In yet another embodiment, the burn-in indicating apparatus comprises a memory device adapted to record the burn-in parameter. The memory device may comprise one or more fuses or, in another configuration, a programmable memory device.
In yet another embodiment, a semiconductor wafer is provided which permits simultaneous burn-in of all the dies on the wafer. The wafer includes one or more conductive pads located in an inactive region of the wafer wherein the conductive pads are adapted to electrically couple to an external power supply. The wafer additionally includes a plurality of dies located in an active region of the wafer and a burn-in indicating apparatus associated with each die of the plurality of dies. The burn-in indicating apparatus is adapted to monitor one or more burn-in parameters. The wafer still further includes scribe areas separating the plurality of dies and one or more conductive rings surrounding each die, wherein the conductive rings are electrically coupled to die bond pads on each die. Scribe conductors are also included and located within the scribe areas. The scribe conductors electrically couple the one or more conductive pads to the one or more conductive rings.
In still yet another embodiment, a semiconductor wafer is provided which permits simultaneous burn-in of all the dies on the wafer. The wafer includes one or more conductive pads located on the wafer, wherein the conductive pads are adapted to couple to an external power supply. A plurality of dies is also included, wherein the plurality of dies has one or more circuits. Substantially each die of the plurality of dies also includes: a burn-in indicating apparatus adapted to monitor one or more burn-in parameters; and die bond pads on a face of the die. The die bond pads electrically couple to the one or more circuits and the burn-in indicating apparatus and further electrically coupled to the one or more conductive pads.
In still yet another embodiment, a method for simultaneous burn-in of substantially all the dies on a semiconductor wafer is provided. The method includes: fabricating a semiconductor wafer where the wafer includes a plurality of dies and one or more conductive pads electrically coupled to one or more respective die bond pads located on the plurality of dies. The method further includes connecting an external power supply to the one or more conductive pads to supply power to the plurality of dies and delivering power to the plurality of dies. The method still further includes monitoring one or more burn-in parameters with a burn-in indicating apparatus coupled to each die.
The present invention further provides an IC die, which in one embodiment, includes a burn-in indicating apparatus where the burn-in indicating apparatus is adapted to monitor one or more burn-in parameters. The IC die further includes die bond pads on a face of the die, wherein the die bond pads are electrically coupled to the burn-in indicating apparatus.
Although briefly summarized here, the invention can best be understood by reference to the drawings and the description of the embodiments which follow.
REFERENCES:
patent: 4768073 (1988-08-01), Adams
patent: 5047711 (1991-09-01), Smith et al.
patent: 5053700 (1991-10-01), Parrish
patent: 5389556 (1995-02-01), Rostoker et al.
patent: 5442282 (1995-08-01), Rostoker et al.
patent: 5489538 (1996-02-01), Rostoker et al.
patent: 5504369 (1996-04-01), Dasse et al.
patent: 5532174 (1996-07-01), Corrigan
patent: 5539325 (1996-07-01), Rostoker et al.
patent: 5593903 (1997-01-01), Beckenbaugh et al.
patent: 5600257 (1997-02-01), Leas et al.
patent:
Bell James W.
Fenner Andreas A.
Fulton Daniel E.
Gerrish Paul F.
Larson Lary R.
McDowall Paul H.
Medtronic Inc.
Nguyen Dilinh
Pham Long
Wolde-Michael Girma
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