Circuit for shifting switching signals

Details Circuit for shifting switching signals Circuit for shifting switching signals

2002-03-18

2003-04-29

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S070000, C326S083000

Reexamination Certificate

active

06556047

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronic circuits, such as monolithic integrated circuits using CMOS technology, and in particular, to a circuit for shifting switching signals.
BACKGROUND OF THE INVENTION
The function of a shifting circuit is to generate output switching signals which are in phase and/or in phase opposition with input switching signals, but whose voltage levels associated with the high and low logic states are different from (in general higher than) the respective voltage levels for the input switching signals. Such a circuit, also known as a translation circuit, may be applied as an interface circuit between modules operating with switching signals having different voltage levels.
Such a circuit, made using CMOS technology, for example, is shown in
FIG. 3
of European Patent No. 789,456. The disclosed circuit comprises a bistable circuit formed of two branches comprising a pair of respective N-type MOS transistors whose sources are linked to ground, and a first pair of respective P-type MOS transistors whose sources are linked to a positive supply voltage. The drain of one of the MOS transistors is connected to the gate of the other MOS transistor, and vice versa. A second pair of respective P-type MOS transistors, having their gates brought to a given voltage is interposed between the abovementioned N-type and P-type MOS transistors.
Furthermore,
FIG. 4
of the referenced European patent discloses means for accelerating the switching of the bistable circuit. These means comprise a third pair of P-type MOS transistors, whose sources are brought to the positive supply voltage, whose drains are linked to the drains of the P-type MOS transistors of the second pair, and whose gates are controlled by a logic element so as to charge the parasitic capacitances of the P-type MOS transistors of the first pair during the switching phases.
The switching of the bistable circuit is thus accelerated. However, this logic element is complex to make and involves many logic gates, thereby increasing the area occupied by the level shifting circuit on the silicon substrate, and increasing the consumption of current.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to remedy the drawback of the prior art by accelerating the switching of the bistable circuit in a relatively straightforward manner, and which therefore occupies less area on a silicon substrate.
This and other objects, advantages and features of the present invention are provided by a circuit for shifting at least one switching signal, with the circuit comprising a bistable circuit with two branches. The circuit is preferably formed using CMOS technology. Each branch is connected between a first terminal delivering a first positive supply voltage, and a second terminal delivering a second negative or zero supply voltage.
Each branch comprises an input transistor and an output transistor. The drain of the output transistor of each branch is linked to the gate of the output transistor of the other branch. The drain of the output transistor of each branch is linked to the drain of the input transistor of the same branch through at least one first voltage clamping transistor.
The circuit further comprises means for accelerating the switching of the bistable circuit for allowing the output transistor of each branch to be switched to the off state when the input transistor of this branch switches to the on state. The means for accelerating switching comprise, for at least one given branch, an associated current mirror generating a turn-off current for the output transistor of the branch on the basis of a turn-on current for the input transistor of the branch.
The means for accelerating switching are therefore relatively straightforward since they are reduced to one current mirror, or two current mirrors, i.e., one per branch. Since a current mirror comprises only four transistors, the means occupy a reduced area on the silicon substrate.


REFERENCES:
patent: 4703199 (1987-10-01), Ely
patent: 5045721 (1991-09-01), Yan
patent: 5736869 (1998-04-01), Wei
patent: 5936432 (1999-08-01), Oh et al.
patent: 6064227 (2000-05-01), Saito
patent: 6232794 (2001-05-01), Cox
patent: 6249169 (2001-06-01), Okada
patent: 0789456 (1996-02-01), None

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