Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1998-09-16
2003-04-29
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S151000, C711S158000, C711S168000
Reexamination Certificate
active
06557085
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention is in the electronics field. More specifically, the invention relates to a circuit configuration for handling and resolving access contentions in memories with a plurality of mutually independent I/O ports that can be simultaneously addressed in parallel.
Future microelectronic circuits will realize complicated systems with transistors numbering between 10
12
and 10
15
. Those systems, such as, for example, parallel processor systems, artificial intelligence systems, or multimedia systems, will, as a rule, contain a plurality of cooperating subsystems for processing data. A crucial problem for efficient practical realization of those systems will thus be the storage of the data to be processed and also of the data processing programs. The most powerful systems will surely be able to be realized when a memory is available which the subsystems can access temporally in parallel and with a high bandwidth.
An attractive solution to this problem is the use of so-called multi-port memories, which have a multiplicity of independent connection ports which external assemblies can access temporally in parallel.
However, access contentions can arise in all multi-port memories having independently addressable ports. An access conflict or access contention arises when two or more ports wish to access the same memory cell simultaneously. Whether such an access contention arises only during write operations or else during write/read operations depends on the chosen memory architecture. In conventional multi-port memories, in which all of the connection ports are implemented in each of the memory cells, an access contention arises exclusively during a write access. In multi-port memories which have one-port memory cells, such as, for example, a so-called switching network or a hierarchically constructed memory architecture, an access contention arises both during a write access and during a read access.
The above-described problem of access contention rarely manifested itself in the past since multi-port memories having mutually independently addressable ports have rarely been used to date in integrated systems.
In systems in which multi-port memories were nevertheless used, an access contention was usually resolved at the system end. This means that an access contention was identified by the system containing the multi-port memory and an assignment of the data was made program-specifically for each port. Thus, the memory itself was not provided with any dedicated means for handling access contentions. Consequently, additional circuitry and/or programming complexity was necessary at the system end in order to operate a multi-port memory of this type.
In a further approach for handling access contentions in multi-port memories, the various external connection ports were switched internally to a single port. In the event of an access contention, which always arises in the event of simultaneous access by a plurality of ports, the data were processed sequentially, for example by a simple multiplexer and a small buffer store, via the single internal connection port. Consequently, however, a multi-port memory of this type has the operating behavior of a one-port memory.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for handling access contentions in multi-port memories, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for handling access contentions in a memory with a plurality of mutually independent, simultaneously addressable I/O ports, comprising:
at least one contention identification circuit for identifying an access contention between a plurality of I/O ports to a given memory cell of a memory; and
at least one contention inhibit circuit connected to the contention identification circuit, the contention inhibit circuit, in event of an access contention between a plurality of I/O ports to the given memory cell, generating output signals enabling one of the plurality of I/O ports involved in the access contention and inhibiting all other I/O ports involved in the access contention.
The inventive circuit configuration for handling access contentions is in this case contained as a subcircuit in a multi-port memory. In the event of an access contention, i.e. an access conflict between two or more ports, the circuit configuration for handling access contentions decides the port by which the access can be effected and the port or ports for which the access is rejected.
The novel circuit configuration comprises two subcircuits: the so-called contention identification circuit and the so-called access inhibit circuit.
In accordance with an added feature of the invention, the contention identification circuit generates a status signal specifying the plurality I/O ports involved in the access contention exists and the contention inhibit circuit receives the status signal from the contention identification circuit. The contention inhibit circuit allocates a priority to each of the ports which are involved in the access contention. Based on this prioritization, the highest prioritized port is enabled, while the remaining ports are inhibited. The status of each port, that is to say whether or not the respective access was successful, is indicated in a second status signal for the entire system containing the multi-port memory.
In accordance with an additional feature of the invention, the contention inhibit circuit is adapted to prioritize the I/O ports in accordance with an importance thereof defined by a prioritization algorithm. Two preferred algorithms are presented herein, namely a so-called PIH algorithm and a so-called “fair” IPIH algorithm.
In accordance with another feature of the invention, the contention identification circuit includes a plurality of multi-input EXOR gates performing logic combination of the addresses for selecting the I/O ports involved in the access contention.
With the above and other objects in view, the circuit is provided in combination with a memory device having a memory architecture constructed in multi-level hierarchy.
The system is also provided in combination with a memory device having a memory architecture constructed from multi-port memory cells.
In accordance with a concomitant feature of the invention, the multi-port memory architecture operates according to the switching network principle.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for handling access contentions, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
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“Speicherkonfigurationen mit Dual-Port-SRAMs”, Hans Bliklen, Design & Elektronik, vol. 12, Jun. 1987, p. 106 and 108.
“Multi-Port Dynamic Random Access Memory Controller”, IBM Technical Disclosure Bulletin, vol. 34, No. 2, Jul. 1991, pp. 495-498.
Peugh Brian R.
Yoo Do Hyun
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