Method of improving gate activation by employing atomic...

Details Method of improving gate activation by employing atomic... Method of improving gate activation by employing atomic...

2001-07-13

2003-05-20

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S306000, C257S344000

Reexamination Certificate

active

06566210

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor device fabrication, and more particularly to a method of fabricating Si-based metal-insulator-semiconductor (MIS) transistors comprising at least a Si-containing semiconductor polycrystalline gate conductor, e.g., polysilicon, SiGe, or SiGeC, wherein the gate conductor has grain sizes of about 0.1 &mgr;m or less.
BACKGROUND OF THE INVENTION
Modem Si-based metal-insulator-semiconductor (MIS) field effect transistors (FETs) containing polysilicon gate conductors are typically fabricated with the use of socalled sidewall or comer oxidation of the gate comer. Sidewall oxidation processes are routinely employed in conventional process flows such as complementary metal oxide semiconductor (CMOS) logic, static random access memory (SRAM), dynamic random access memory (DRAM), embedded DRAM, flash memories and other like processing flows.
As is known to those skilled in the art, sidewall oxidation of the gate comers thickens the gate insulator at the gate comer. Thick comer insulators prevent electrical breakdown at the device comers. The comer insulator also reduces the electric field by effectively rounding the comer during oxidation. A higher comer electric field can produce large hot-carrier effects leading to poor transistor reliability. In addition, the planar oxide grown during comer oxidation is used as a screen oxide for a subsequent ion-implantation step, thus, simplifying process integration flow. All these benefits of sidewall (or comer) oxidation are well known in the art; therefore a detailed discussion concerning the same is not needed herein.
As also known to those skilled in the art, semiconductor devices comprising polysilicon gate conductors having small grain sizes (on the order of about 0.05 &mgr;m or less) are preferred over devices wherein the polysilicon gate conductors have large grain sizes. This is because; devices containing polysilicon having small grain sizes have the following benefits associated therewith:
(1) Dopant diffusion from the implanted area to the polysilicon/gate dielectric interface will be faster because the density of the grain boundaries is higher; the concentration of the dopants will be higher at the interface and this will improve gate activation.
(2) There will be at least one vertical grain boundary path for small gates (less than 0.05-0.1 &mgr;m). With large grains, there is the possibility that no grain boundary paths exist between the top and the bottom of the gate. This can prevent dopants reaching the bottom interface and can cause severe poly depletion problems in small devices.
(3) Dopants have to diffuse shorter distances within the grains to completely dope the interior of the grains. This can increase the activation in the polysilicon gate conductor since dopants are only active inside the grains.
To reap all of the above-mentioned benefits, the grain size should be kept as small as possible until the dopants are implanted into the gate. However, in current technologies, sidewall oxidation is generally performed before the implantation of the dopants into the gate. Sidewall oxidation usually has a high thermal budget associated therewith. Due to the high thermal budget, grain size can increase significantly during the sidewall oxidation process.
In order to prevent the above from occurring, the sidewall oxidation thermal budget needs to be reduced. To date, the inventors are unaware of any prior art process that sufficiently addresses the above-mentioned problems. Hence, there is a continued need for developing a new and improved method for fabricating Si-based MIS transistors comprising polysilicon or other Si-containing semiconductor polycrystalline gate conductors having small grain sizes associated therewith in which the method significantly reduces the thermal budget of the sidewall oxidation process.
SUMMARY OF THE INVENTION
One object of the present invention relates to a method of fabricating a Si-based MIS transistor comprising a Si-containing semiconductor polycrystalline gate conductor having small grain sizes associated therewith. The term “small grain sizes” as used herein denotes grains whose size is about 0.1, preferably 0.05, &mgr;m or less. The term “Si-containing semiconductor polycrystalline gate conductor” includes polysilicon, SiGe, SiGeC, Si/SiGe and other like materials.
A further object of the present invention is to provide a method of fabricating a Si-based MIS transistor in which the thermal budget of the sidewall oxidation process is significantly reduced so as to maintain the small grain sizes within the gate conductor.
A yet further object of the present invention is to provide a method of fabricating a Sibased MIS transistor which minimizes the poly depletion effects that are typically observed in prior art Si-based MIS transistors.
An even further object of the present invention is to provide a method of fabricating a Si-based MIS transistor which prevents the grains of the gate conductor from getting larger by reducing the thermal budget of the sidewall oxidation process utilizing a process which is easy to implement with existing technologies.
These and other objects and advantages are achieved in the present invention by utilizing atomic oxygen as the oxidative ambient during the sidewall gate oxidation step. The use of atomic oxygen during sidewall oxidation has unexpectedly reduced the thermal budget of the oxidation process by a factor of one or two orders of magnitude as compared with typical thermal budgets obtained by prior art sidewall oxidations. The lowering of the thermal budget of the sidewall oxidation process results in the formation of a Si-based MIS transistor comprising a Si-containing semiconductor polycrystalline gate conductor whose grain sizes are about 0.1, preferably 0.05, &mgr;m or less.
Specifically, the method of the present invention comprises the steps of:
(a) forming a structure comprising a patterned Si-containing semiconductor polycrystalline region with grains of less than about 0.1 &mgr;m a surface of a gate dielectric, said gate dielectric being formed on a surface of a Si-containing substrate;
(b) subjecting said structure to a sidewall oxidation process in which atomic oxygen is employed so as to oxidize a portion of said Si-containing semiconductor polycrystalline region;
(c) implanting dopant ions into said Si-containing substrate and said Si-containing semiconductor polycrystalline region; and
(d) activating said dopant ions.
Another aspect of the present invention relates to a Si-based MIS transistor which is formed by the above-mentioned method. Specifically, the inventive Si-based MIS transistor comprises:
a Si-containing substrate;
a gate dielectric formed on a surface of said Si-containing substrate;
a patterned region of doped Si-containing semiconductor polycrystalline material formed on a surface of said gate dielectric, wherein said region of doped Si-containing polycrystalline material has grain sizes of about 0.1 &mgr;m or less;
a layer of thermal oxide formed on at least sidewalls of said patterned region of doped Si-containing semiconductor polycrystalline material; and
diffusion regions formed in said Si-containing substrate about said patterned region of Si-containing semiconductor polycrystalline material, wherein said diffusion regions are in electrical contact with each other via a channel region.


REFERENCES:
patent: 5998289 (1999-12-01), Sagnes
patent: 6219299 (2001-04-01), Forbes et al.

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