Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-19
2003-07-22
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S262000, C438S279000, C438S287000, C438S294000, C438S295000, C438S296000, C438S297000, C438S299000, C438S301000
Reexamination Certificate
active
06596584
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of electronic devices and more particularly to a method for fabricating a self-aligned source line flash memory device.
BACKGROUND OF THE INVENTION
Most modern electronic equipment, such as phones and computers, are generally constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are generally constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductive, semiconductive, and insulative regions formed on the semiconductor substrate.
FLASH memory, also known as FLASH EPROM or FLASH EEPROM, is a semiconductor component that is formed from an array of memory cells. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each cell includes a floating gate transistor having a source, a drain, a floating gate, and a control gate. The floating gate transistor uses channel hot electrons for writing from the drain and uses Fowler-Nordheim tunneling for erasure from the source. The source of each floating gate transistor in the cells of a row in the array are connected to form a source line.
The cells are electrically isolated from one another by an isolation structure. One type of isolation structure used is a LOCal Oxidation of Silicon (LOCOS) structure. LOCOS structures are generally formed by thermally growing a localized oxidation layer between the cells to electrically isolate the cells. Another type of isolation structure used is a Shallow Trench Isolation (STI). STI structures are generally formed by etching a trench between the cells and filling the trench with a suitable dielectric material.
Some source line fabrication processes utilize a patterned photomask that exposes a source region of the semiconductor substrate as well as a portion of the floating gate transistors in the array. The exposed areas are subsequently anisotropically etched and then subjected to an ion implantation process that forms the source line and the self-aligned source for each floating gate transistor. Although the etching process is non-selective to the materials comprising the semiconductor substrate and the floating gate transistor and the field oxide, the etching process removes a portion of the exposed semiconductor substrate and the floating gate transistor along with the desired removal of the field oxide region to form the continuous source line.
The removed portion of the semiconductor substrate generally forms a trench in the source line region between the floating gates. The trench adversely affects the performance of the floating gate transistor due to the depth difference between the floating gate and the source line. This depth difference can result in a source-to-drain short of the floating gate transistor. The depth difference also lowers the dopant concentration in the source adjacent the floating gate transistor. The low dopant concentration can result in erase errors during operation of the memory array.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an improved source line fabrication process for flash memory. The present invention provides a method for fabricating a self-aligned source line for a flash memory device that substantially eliminates or reduces problems associated with the prior methods.
In accordance with the one embodiment of the present invention, a method for fabricating a flash memory device having a self-aligned source includes providing a semiconductor substrate having a source region separated from a drain region by a channel region. The method also includes forming an isolation structure in the semiconductor substrate that crosses the source, drain, and channel regions of the semiconductor substrate. The method also includes forming a continuous stack structure outwardly from the channel region of the semiconductor substrate and the isolation structure. The method includes depositing a bottom anti-reflective layer over the semiconductor substrate, the isolation structure and the stack structure to substantially uniformly planarize the semiconductor substrate and the isolation structure. The method further includes depositing a photoresist layer over select portions of the bottom anti-reflective layer and the continuous stack structure to form a self-aligned source pattern using a photo mask. The method includes etching the isolation structure and the bottom anti-reflective layer corresponding to the self aligned source pattern using a low selectivity etch process to remove a portion of the isolation structure and etching a remaining portion of the isolation structure using high selectivity etch process.
Important technical advantages of the present invention include fabricating a source line that has minimum or no trenching in the source line region compared to the bottom of the floating gate. This reduces the stress on the floating gate transistor and can reduce the likelihood of a source-to-drain short in the transistor. Accordingly, the present invention substantially reduces the likelihood of transistors within the memory array that are non-functional. Another technical advantage of the present invention includes greater uniformity and concentration of dopant within the source region adjacent the floating gate transistor.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5210047 (1993-05-01), Woo et al.
patent: 6071779 (2000-06-01), Mehrad et al.
patent: 6087220 (2000-07-01), Rogers et al.
patent: 6180460 (2001-01-01), Cremonesi et al.
Chintapalli Paul A.
Gunturi Sarma S.
Brady III W. James
Elms Richard
Luu Pho M.
McLarty Peter K.
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