Method of forming a metal oxide semiconductor transistor...

Details Method of forming a metal oxide semiconductor transistor... Method of forming a metal oxide semiconductor transistor...

2002-04-26

2003-09-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S525000, C438S692000

Reexamination Certificate

active

06620692

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to metal oxide semiconductor (“MOS”) transistors and are more particularly directed to such a transistor with a self-aligned channel implant.
Electronic circuit design is often critically affected by the design of individual transistors used within a circuit. As a result, transistor design has developed for years and continues to be an area of extensive research for various issues, including uniformity of operation between multiple transistors constructed according to a same design as well as device reliability. In this regard, MOS field effect transistor (“MOSFET”) design typically specifies parameters and methods relating to the formation of various components relative to a semiconductor substrate, including the creation of doped regions within the substrate. Consequently, these parameters and methods affect aspects such as operational uniformity and reliability.
One aspect of a MOSFET where the above considerations is implicated is in the formation of the transistor channel, which as known in the art is the area in which a current may be induced to flow between the source and drain of the transistor. The locations of the regions that define the channel, as well as the length of the channel, may affect operational uniformity and reliability as well as other aspects relating to the transistor. Channel length may be an issue in various transistors, including one type of known MOSFET referred to in the art as a drain extended MOS (“DEMOS”) transistor. A DEMOS transistor is detailed later but is also introduced here by way of background. A DEMOS transistor is named due to having a drain region formed from two regions, a first region having a doping level comparable to that of the transistor source and a second region having a reduced doping level and which extends under the transistor gate. DEMOS transistors are used in various circuits, where one instance is a circuit that has different operating voltages such as where a first voltage is used at the input/output level while a second and lower voltage is used for the operational core of the circuit. In these cases, transistors suitable for use at the higher input/output voltages are required, and one type of such a transistor is the DEMOS transistor. DEMOS transistors also may be used in applications where the voltage on the drain exceeds the normal voltage rating of the gate oxide.
Given the preceding, it has been observed by the present inventors that for the DEMOS transistor, and possibly for other MOSFETs, some approaches in the art form regions that define the transistor channel prior to the formation of the transistor gate. For example, for the DEMOS transistor the channel may be defined relative to an insulating region which generally defines the transistor active region. However, often such designs leave room for variation in the channel length as well as the actual formation of the channel, where both aspects may be affected by the later-formed transistor gate. Consequently, these variations may affect device uniformity and reliability. The preferred embodiments seek to improve upon these drawbacks, as further explored below.
BRIEF SUMMARY OF THE INVENTION
In the preferred embodiment, there is a transistor. The transistor comprises a gate conductor and a gate insulator separating the gate conductor from a semiconductor material having a first conductivity type. The transistor further comprises a drain region having the first conductivity type. The transistor further comprises an angular implanted region having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge underlying the gate conductor, and the transistor includes a source region formed within the angular implanted region. Finally, a transistor channel is defined between an edge of the source region proximate the gate conductor and the angular implanted region edge underlying the gate conductor. Other aspects are also disclosed and claimed.


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patent: 5316961 (1994-05-01), Okazawa
patent: 5642295 (1997-06-01), Smayling
patent: 6261964 (2001-07-01), Wu et al.
patent: 6268640 (2001-07-01), Park et al.
patent: 6444548 (2002-09-01), Divakaruni et al.

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