Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-05
2003-05-06
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000
Reexamination Certificate
active
06559016
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a low-leakage, high-performance device.
2. Description of Related Art
The trend in the development of very large scale integration (VLSI) circuits is the production of devices having smaller line width on a larger silicon chip. Hence, more functions can be integrated into an integrated circuit of a given size and production cost can be reduced. The characteristics of a metal-oxide-semiconductor transistor also change somewhat when the device is miniaturized. For example, operating speed of a transistor will increase when length of device channel is reduced.
However, miniaturization of device also brings the source and the drain terminals closer to each other. The depletion region in the source and the drain terminal formed when the MOS transistor is operating often results in some overlapping with the device channel. The shorter the channel, the greater will be the degree of overlapping of the depletion region in the source and the drain terminal with the channel. Aside from overlapping with the channel, a phenomenon known as hot electron effect also affects the operation of the MOS transistor when channel length is reduced. To resolve the problems, the most common method is to form a lightly doped drain (LDD) structure. Nevertheless, the formation of LDD is only good for device having a line width bigger than about 0.25 &mgr;m. In general, the method is useless in preventing the high leakage current that occurs in a device with a very short channel.
FIGS. 1A and 1B
are schematic cross-sectional views showing the progression of steps for manufacturing a conventional low-leakage, high-performance device.
As shown in
FIG. 1A
, a gate electrode
102
is formed over a substrate
100
. A lightly doped drain (LDD) implantation
104
of the substrate
100
is carried out to form a lightly doped drain terminal
106
in the substrate
100
. A halo implantation
108
is next carried out to form a locally doped pocket
110
in the substrate
100
under the lightly doped drain terminal
106
on each side of the gate electrode
102
. When line width of the device is smaller than 0.25 &mgr;m, a dosage greater than 10
15
ions/cm
2
is used in the implantation
104
.
As shown in
FIG. 1B
, spacers
112
are formed on the sidewalls of the gate electrode
102
. A deep-penetration source/drain terminal implantation
114
is conducted to form a source/drain terminal
116
.
FIG. 1C
is a cross-sectional diagram showing in detail the structure after a thermal treatment of the device shown in FIG.
1
B. As shown in
FIG. 1C
, a silicon chip must undergo a thermal treatment after implantation to compensate for the amorphization that occurred near the surface of the chip. However, the thermal treatment will result in a greater range of diffusion for the ions, especially when the lightly doped source/drain terminal
106
is implanted using a dosage of about 10
15
ions/cm
2
. Ultimately, the lightly doped source/drain terminals
106
a
will overlaps considerably with the gate electrode
102
.
In the aforementioned method of forming a MOS transistor, the high concentration LDD terminals often result in large overlapping with the gate after a thermal treatment. Too much overlapping may lead to a shortening of the channel between the source/drain terminals resulting in short-channel effect. To reduce overlapping, the obvious method is to reduce dopant concentration inside the LDD terminals. Yet, too little dopants may increase parasitic capacitance and ultimately lead to greater RC delay.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a low-leakage, high-performance device capable of reducing overlapping between the lightly doped drain (LDD) terminals and the gate of the device due to a high dopant concentration in the LDD terminals, and at the same time also capable of reducing parasitic capacitance and hence RC delay due to a low dopant concentration in the LDD terminals.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a low-leakage, high-performance device. A substrate having a gate electrode thereon is provided. A lightly doped drain (LDD) implantation is conducted to form a lightly doped source/drain terminal in the substrate. An offset spacer is formed on each sidewall of the gate electrode. A heavy dopant implantation is conducted to form a heavily doped source/drain terminal in the substrate. The heavily doped source/drain terminal has a depth smaller than the lightly doped source/drain terminal. A protective spacer structure is formed on each sidewall of the gate electrode. Finally, a deep-penetration source/drain implantation is carried out to form a deep source/drain terminal in the substrate.
In addition, a halo implantation can be carried out after the lightly doped drain implantation to form a locally doped pocket on each side of the gate electrode under the LDD terminal. Similarly, a halo implantation can be carried out after the heavy dopant implantation to form a locally doped pocket on each side of the gate electrode under the LDD terminal.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4356623 (1982-11-01), Hunter
patent: 5580799 (1996-12-01), Funaki
patent: 6190981 (2001-02-01), Lin et al.
patent: 6218226 (2001-04-01), Lin et al.
patent: 6238960 (2001-05-01), Maszara et al.
patent: 6258680 (2001-07-01), Fulford et al.
patent: 6261913 (2001-07-01), Akram et al.
patent: 6281062 (2001-08-01), Sanchez
Lin Tony
Tseng Hua-Chou
Booth Richard
United Microelectronics Corp.
Wu Charles C.H.
Wu & Cheung, LLP
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