Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-23
2003-03-04
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S243000, C438S244000, C438S245000, C438S386000, C438S396000, C438S241000, C438S399000, C438S675000, C438S639000, C438S238000, C438S256000
Reexamination Certificate
active
06528366
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods of fabricating a metal-insulator-metal capacitor, and more particularly, to methods of forming vertical metal-insulator-metal capacitors for embedded DRAM applications in the fabrication of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are critical components in the integrated circuit devices of today. These passive components are often to be integrated with active bipolar or MOS transistors for analog and digital circuits. Capacitors of the types: polysilicon-insulator-polysilicon (PIP), polysilicon-insulator-polycide, polysilicon-insulator-metal (MIS), and metal-insulator-metal (MIM) capacitors have been used in the art. All of these capacitors are planar in nature for CMOS process compatibility and simplicity. The following references discuss such capacitors: “High Performance MIM Capacitor for RF BiCMOS/CMOS LSIs” by T. Yoshitomi et al,
IEEE Bipolar/BiCMOS Circuits and Technology Meetings
, paper #8.2, p. 133, 1999; “SOI CMOS With High-Performance Passive Components for Analog, RF, and Mixed-Signal Design”, by M. Stuber et al,
Proceedings
1998
IEEE International SOI Conference
, p. 99-100, 1998; and “Integrated RF and Microwave Components in BiCMOS Technology”, by J. N. Burghartz et al,
IEEE Trans. on Electron Devices
, V. 43, No. 9, p. 1559-1570, 1996. U.S. Pat. No. 5,998,264 to Wu discloses a MIM capacitor and U.S. Pat. No. 5,918,120 to Huang teaches a capacitor over bit line (COB) process.
Three-dimensional (3-D) MIM capacitors have also been used in advanced DRAM Technology. For example, see “Highly Reliable MIM Capacitor Technology Using Low Pressure CVD-WN Cylinder Storage-Node for 0.12 &mgr;m-scale Embedded DRAM”, by S. Kamiyama et al,
Symposium on VLSI Technology
, paper #4A-4, p. 39-40, 1999, “A DRAM Technology Using MIM BST Capacitor for 0.15 &mgr;m DRAM Generation and Beyond”, by K. Kim et al,
Symposium on VLSI Technology
, paper #4A-1, p. 33-34, 1999, and “Shared Tungsten Structures for FEOL/BEOL Compatibility in Logic-Friendly Merged DRAM” by J. M. Drynan et al,
IEDM
1998, p. 31.6.1-4. The 3-D capacitors often have very small size, have a cylinder or crown shape, use high dielectric constant (k) dielectrics such as Ta
2
O
5
or BST, and are fabricated by complicated DRAM processes. However, these 3-D MIM capacitors are usually fabricated below the first level of metal interconnect which leads to difficulty in merging DRAM and logic due to unmatched front-end and back-end layers. This fact also introduces critical issues including DRAM -logic height differences and high aspect ratio contacts. U.S. Pat. No. 6,117,725 to Huang teaches an embedded DRAM process where the capacitor is formed at the first level of metal interconnect.
In recent studies of embedded DRAM (that is, merging DRAM and logic circuits onto one chip), there have been suggestions to fabricate DRAM capacitors between the first and second levels of metal interconnect. See “Merged DRAM-Logic in the Year 2001” by P. W. Diodato et al,
IEEE Transactions
, 1998 and “A Simple Embedded DRAM Process for 0.16 &mgr;m CMOS Technologies” by C. T. Liu et al,
Symposium on VLSI Technology
, 2000, p. 60-61. However, the global topology between metal-1 and metal-2 results in different via depths. The capacitor height is also fixed in these proposals.
It is desired to provide a method for forming a vertical MIM capacitor for advanced DRAM applications that can be fabricated between any level of metal interconnect, depending on the desired depth of the capacitor, without global topology variation in any interconnect level.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-metal capacitor.
Another object of the present invention is to provide a method for fabricating a vertical metal-insulator-metal capacitor at any level of metal interconnect.
Yet another object of the present invention is to provide a method for fabricating a vertical metal-insulator-metal capacitor at any level of metal interconnect where there is no global topology variation in any interconnect level.
A further object is to provide a method for fabricating a vertical metal-insulator-metal capacitor where the process temperature is low enough so as not to damage or degrade back-end metal interconnects.
A still further object is to provide a method for fabricating a vertical metal-insulator-metal capacitor for embedded DRAM applications.
Yet another object of the invention is to provide a method for fabricating a vertical metal-insulator-metal capacitor for embedded DRAM or mixed-signal applications.
In accordance with the objects of this invention, a method for fabricating a vertical metal-insulator-metal capacitor is achieved. A plurality of contact plugs are formed through an insulating layer to semiconductor device structures in a semiconductor substrate wherein contact plugs are formed in a logic area of the semiconductor substrate and in a memory area of the semiconductor substrate. A plurality of metal lines and via plugs are formed through a plurality of insulating layers vertically contacting one another and contacting the contact plugs in the logic area wherein the insulating layers are also deposited vertically in the memory area. An oxide layer is deposited overlying the topmost of the metal lines and via plugs in the logic area and the topmost insulating layer in both the logic and memory areas. Openings are patterned through the oxide layer and the insulating layers in the memory area whereby a top portion of the contact plugs in the memory area is exposed. A first conducting layer is deposited conformally within the openings and contacting the exposed top portion of the contact plugs wherein the first conducting layer and the exposed contact plugs in the memory area together form a capacitor bottom plate electrode. The openings are partially filled with a protective layer and a top portion of the first conducting layer on upper sidewalls of the openings is etched back. The protective layer is removed. A capacitor dielectric layer is deposited overlying the first conducting layer. A second conducting layer is deposited overlying the capacitor dielectric layer. The second conducting layer and capacitor dielectric layer are removed except within the openings to complete formation of a vertical MIM capacitor in the fabrication of an integrated circuit device.
Also in accordance with the objects of this invention, another method for fabricating a vertical metal-insulator-metal capacitor is achieved. A plurality of contact plugs is formed through an insulating layer to semiconductor device structures in a semiconductor substrate wherein the contact plugs are formed in a logic area of the semiconductor substrate and in a memory area of the semiconductor substrate. A plurality of metal lines and via plugs are formed through a plurality of insulating layers vertically contacting one another and contacting the contact plugs in said both the logic area and the memory area. An oxide layer is deposited overlying the topmost of the metal lines and via plugs in both logic and memory areas. The oxide layer is removed where the capacitor is to be formed in the memory area. The plurality of metal lines and via plugs not covered by the oxide layer in the memory area are removed whereby openings are left exposing the contact plugs at the bottom of said openings in the memory area. A first conducting layer is deposited conformally within the openings contacting the exposed contact plugs wherein the first conducting layer and the exposed contact plugs in the memory area together form a capacitor bottom plate electrode. The openings are partially filled with a protective layer and a top portion of the first conducting layer on upper sidewalls of the openings is etched back. The protective layer is removed. A capacitor dielectric layer is deposited overlying the first conducting layer. A second co
Chi Min-Hwa
Lin Dah
Tu Yeur-Luen
Ackerman Stephen B.
Chaudhuri Olik
Nguyen Khiem D
Pike Rosemary L. S.
Saile George O.
LandOfFree
Fabrication methods of vertical metal-insulator-metal (MIM)... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication methods of vertical metal-insulator-metal (MIM)..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication methods of vertical metal-insulator-metal (MIM)... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3029802