Method of using trenching techniques to make a transistor...

Details Method of using trenching techniques to make a transistor... Method of using trenching techniques to make a transistor...

2001-08-16

2003-07-01

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S260000, C438S261000, C438S262000, C438S263000, C438S264000, C438S593000, C438S594000

Reexamination Certificate

active

06586302

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of using trenching techniques to fabricate a transistor having a floating gate.
BACKGROUND OF THE INVENTION
Non-volatile reprogrammable semiconductor memory devices which utilize a floating gate are well known in the art. One such type of semiconductor memory device is shown in U.S. Pat. Nos. 5,029,130; 5,045,488; 5,067,108; 5,242,848; and 5,278,087. These patents are incorporated herein by reference. These patents disclose a structure for a programmable and erasable memory cell that utilizes a single transistor, which is often referred to as a “split gate” cell.
FIG. 1
shows a cross sectional view of the split gate memory cell of the prior art. The operation of this semiconductor device
50
is discussed in detail in the patents referred to above. A general summary of the structure of the split gate cell
50
is provided as follows. Source region
106
and drain region
102
are disposed in a semiconductor substrate
20
. The drain region
102
is formed adjacent to the one edge of the control gate
100
. The source region
106
is formed to have at least a portion of the region beneath the floating gate
108
. The floating gate
108
is positioned underneath a portion of the control gate
100
. A dielectric material is disposed between the floating gate
108
, the control gate
100
, and the substrate
20
.
As is well known, the memory cell device can be operated in three modes: erase, program, and read. In the erase mode, a positive erase voltage is applied to the control gate
100
. Depending on the design of the device
50
, the range of the erase voltage can vary. Typically, an erase voltage in the range of 10 volts is utilized. The source
106
and the drain
102
are then brought to ground. The floating gate
108
is thereby capacitively coupled with the source
106
, which results in the voltage of the floating gate
108
initially being very close to that of the source
106
, which is significantly less than the erase voltage applied to the control gate
100
. As a result of the potential difference between the floating gate
108
and the control gate
100
, electrons on the floating gate
108
will move through a dielectric material to the control gate
100
by the mechanism of Fowler-Nordheim tunneling. This tunneling occurs due to the locally enhanced field on the surface of the floating gate, and particularly at the tip of the floating gate
110
. Due to the shape of the floating gate and the thickness of the oxide between the floating gate and the control gate, electrons will tunnel vertically from the tip
110
of the floating gate to the control gate proximate to the tip of the floating gate. After the erase operation has been completed, the floating gate
108
will have a net positive charge, or at minimum will be neutral (non-negative), because many electrons will have moved from the floating gate
108
to the control gate
100
.
The cell
50
is programmed as follows. A programming voltage in the range of approximately 10 volts is applied to the source
106
. The voltage applied to the drain
102
is in the range of approximately 1 volt, and the voltage applied to the control gate
100
is in the range of approximately 2 volts. This creates an electric field which causes current to move through the channel
104
. Specifically, electrons will move from the drain
102
toward the source
106
. The voltage in the area
112
of the channel
104
beneath the control gate
100
will be relatively small. In the area
114
of the channel
104
beneath the floating gate
108
, however, there will be a steep increase in voltage. This is due to the fact that there is strong capacitive coupling between the source
106
and the floating gate
108
. This capacitive coupling results in the potential of the floating gate
108
initially being relatively close to the potential of the source
106
. As a result of this steep increase in potential between the region
112
of the channel
104
under the control gate
100
, and the region
114
of the channel
104
under the floating gate
108
, hot electrons are generated some of which will move from the channel
104
onto the floating gate
108
. Thus, after programming, the floating gate
108
will have a net negative charge as a result of the hot electrons which have moved onto the floating gate
108
, thereby identifying the cell
50
as “programmed”.
To read the cell
50
, a voltage in the range of approximately 1 volt is applied to the drain
102
, the source
106
is in the range of approximately 0 volts, or ground, and the control gate
100
is brought in the range of approximately two volts. If the floating gate
108
has a net negative charge as a result of being programmed, than the channel region
114
under the floating gate
108
will be closed and current will not result from the read voltages. If, however, the floating gate
108
has a positive charge, or is neutral, due to the device having been erased, then the region
114
of the channel
104
beneath the floating gate
108
will be opened and current will result. Thus, current flow, or lack of current flow, can be viewed as a binary distinction between memory cells.
This type of memory cell is appropriate for use in a memory device having an array of memory cells, and having circuitry to provide conventional row and column addressing as discussed in the above referenced patents.
As is apparent from the above provided review of the operation of the split gate cell
50
, the shape of the floating gate
108
, and particularly the tips
110
of the floating gate which project toward the control gate, is crucial for promoting efficient tunneling of electrons from the floating gate to the control gate. Specifically, the floating gate tip is used as an electric field enhancing point to assist in Fowler-Nordheim current tunneling, as will be discussed in more detail below. As discussed in the above-referenced patents, a polysilicon oxidation process (LOCOS) can be used to create the tips of the floating gate. The polysilicon LOCOS derived tip, has inherent difficulties associated with it however, specifically in its manufacturability. The poly grain structure and LOCOS birds beak are examples of the causes of its variability. The LOCOS derived tip varies in both radius of curvature, tip angle and distance the tip penetrates into the overlying tunneling oxide. These attributes of the floating gate tip can effect the overall operation of the device.
What is needed is a repeatable and consistent process for making a floating gate. The present invention proposes the use of a STI (shallow trench isolation) type of process to create a floating gate tip. This process leads to enhanced tip profile stability and control.
SUMMARY
The present invention is directed to a method for making a split gate memory cell. In one embodiment the method for producing the memory cell includes depositing a first layer of conductive material above a substrate. Then a trench is created in the first layer of conductive material. After creating the trench, a thermal oxide layer is formed in the trench, and another layer of oxide is deposited over the thermal oxide layer. The oxide in the trench is then used as a mask during an etching process that etches the first layer of conductive material to form a floating gate. After the floating gate has been formed a layer of tunneling oxide is formed over the floating gate. A second layer of conductive material is then deposited over tunneling oxide. This layer of conductive material is then etched to form a control gate.


REFERENCES:
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
patent: 5029130 (1991-07-01), Yeh
patent: 5045488 (1991-09-01), Yeh
patent: 5067108 (1991-11-01), Jenq
patent: 5242848 (1993-09-01), Yeh
patent: 5278087 (1994-01-01), Jenq
patent: 6090668 (2000-07-01), Lin et al.
patent: 6294429 (2001-09-01), Lam et al.
patent: 6300196 (2001-10-01), Chang
patent: 6358797 (2002-03-01), Tseng
patent: 2002/0064910 (2002-05-01), Chen et al.
Technical Paper, “SuperFlash EEPROM

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